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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
oki semiconductor fedl6650full-06 issue date: may 30, 2002 msm6652/53/54/55/56-xxx, msm6652a/53a/ 54a/55a/56a/58a-xxx, msm66p56-xx, msm6650 internal mask rom voice synthesis ic, internal one-time-programmable (otp) rom voice synthesis ic, external rom drive voice synthesis ic 1/126 general description the msm6650 family is the successor to oki?s msm6375 family. to ensure high-quality voice synthesis, the msm6650 family members offer adaptive differential pulse-code modulation (adpcm) playback, pulse-code modulation (pcm) playback, 12-bit d/a conversion, and on-chip ?40 db/octave low-pass filter (lpf). the conventional ?beep? tones and 2-channel playback are now easier to use. oki has added additional functions such as melody play, fade-out, and random playback. oki has improved external control by adding an phrase control table functioin. the phrase control table functi on can be used to form sentences by linking phrases. the msm6650 family members can support a variety of applications as it can function in either standalone mode or microcontroller interface mode. in mi crocontroller interface mode, serial in put control is available. serial input control minimizes the number of microcontroller port pins required for voice synthesis control. the msm6650 family includes an internal mask rom version, internal one-time-programmable (otp) rom version, and external rom version. the features of the msm6650 family devices are as follows. ? msm6652/53/54/55/56-xxx these devices are single-chip voice synthesizers with an on-chip mask rom using the cmos technology. standalone mode or microc ontroller interface mode can be selected by mask option. these have already been obsolete devices. we recommend a version when you design in your new products as bellows. ? msm6652a/53a/54a/55a/56a/58a-xxx the trial production period for these devices is shorter than those described above. these devices are suitable for new products. ? msm66p56-xx the device is a single-chip cmos voice synthesizer with one-time-programmable (otp) rom. standalone and microcontrolle r interface modes are selected by using a code (01-04). the user can easily write voice data using the development tool ar204,ar205. unlike the mask rom version, the otp version is suited to applications which requires a small lot production of different type devices or short delivery time. ? msm6650 the msm6650 device can directly connect external rom or eprom of up to 64 mbits , which stores voice data. this device is ideally suited to an evaluation ic for the msm6650 family because its circuit configuration is identical to those of the mask rom-based and otp version devices.
fedl6650full-06 oki semiconductor msm6650 family 2/126 contents standalone mode features ....................................................................................................................... ...................................... 5 block diagrams ................................................................................................................. ............................ 7 pin configuration (top view) ................................................................................................... .............. 10 pin descriptions ............................................................................................................... ............................ 12 absolute maximu m ratings....................................................................................................... ............ 17 recommended operating conditions ............................................................................................... 17 electrical char acteristics..................................................................................................... ............. 18 timing di agrams ................................................................................................................ .......................... 20 functional description......................................................................................................... .................. 22 1. playback code specifi cation ................................................................................................. ........................ 22 2. internal rom usag e and disabled area ........................................................................................ ............... 22 3. pull-up/pull- down resi stor.................................................................................................. .......................... 22 4. option(s)................................................................................................................... ..................................... 23 5. standalone mode ............................................................................................................. .............................. 23 6. sampling frequency.......................................................................................................... ............................ 29 7. voice pla yback time ......................................................................................................... ............................ 30 8. channel status .............................................................................................................. ................................. 30 9. playback method ............................................................................................................. .............................. 30 10. standby conver sion......................................................................................................... ............................ 33 11. voice output ............................................................................................................... ................................. 33 12. low-pass filter pop noise .................................................................................................. ....................... 35 13. rc osc illatio n ............................................................................................................. ................................ 36 14. ceramic oscilla tion ........................................................................................................ ............................. 40 15. power supply (for msm6650) ................................................................................................. .................. 41 application circuits ........................................................................................................... ....................... 42
fedl6650full-06 oki semiconductor msm6650 family 3/126 microcontroller interface mode features ....................................................................................................................... .................................... 46 block diagrams ................................................................................................................. .......................... 48 pin configuration (top view) ................................................................................................... .............. 51 pin descriptions ............................................................................................................... ............................ 53 absolute maximu m ratings....................................................................................................... ............ 59 recommended operating conditions ............................................................................................... 59 electrical char acteristics..................................................................................................... ............. 60 timing di agrams ................................................................................................................ .......................... 62 functional description......................................................................................................... .................. 68 1. playback code specifi cation ................................................................................................. ........................ 68 2. internal rom usag e and disabled area ........................................................................................ ............... 68 3. pull-up/pull- down resi stor.................................................................................................. .......................... 69 4. options ..................................................................................................................... ..................................... 69 5. microcontroller interface mode .............................................................................................. ...................... 72 6. command data................................................................................................................ .............................. 76 7. address data................................................................................................................ .................................. 84 8. stop code ................................................................................................................... ................................... 85 9. sampling frequency.......................................................................................................... ............................ 90 10. voice play back time ........................................................................................................ ........................... 90 11. channe l status ............................................................................................................. ................................ 91 12. playback meth od ............................................................................................................ ............................. 91 13. standby conver sion......................................................................................................... ............................ 94 14. voice output ............................................................................................................... ................................. 94 15. low-pass filte r pop noise .................................................................................................. ........................ 96 16. ceramic oscilla tion ........................................................................................................ ............................. 97 17. power supply (for msm6650) ................................................................................................. ................... 98 18. external rom drivin g timing (for msm6650) .................................................................................. ....... 99 application circuits ........................................................................................................... ..................... 101 phrase control table function phrase cont rol table........................................................................................................... .................. 105 1. phrase control table commands ............................................................................................... ................. 109 2. pcm playback using th e phrase control table ................................................................................. .......... 113 3. melody playback using the phrase control table .............................................................................. ......... 113 4. random playback using the phrase co ntrol table .............................................................................. ........ 113 5. channel 2 mixing function in the phrase control table....................................................................... ...... 114 echo playback of a single phrase ............................................................................................... .... 114 echo playback of multiple phrases .............................................................................................. .117 echo playback of a single phrase within a phrase string................................................. 118 package dimensions ............................................................................................................. .................... 121 revision history ............................................................................................................... ......................... 125
fedl6650full-06 oki semiconductor msm6650 family 4/126 the table below shows the major differences between the msm6650 family and the msm6375 family. msm6650 family msm6375 family interface standalone mode/microcontroller interface mode sw input/cpu input interface voice synthesis method 4-bit adpcm or 8-bit pcm/melody pcm 4-bit adpcm ?beep? tone frequency (length) 0.5, 1.0, 1.3, 2.0khz options (16 ms to 2100 ms) 1.0 and 2.0 khz, (user-specified length, fixed at either 64, 128, 250, or 500 ms) sampling frequency (f sam ) eight frequencies (4.0,5.3, 6.4, 8.0, 10.6, 12.8, 16.0, or 32.0 khz) three frequencies at two oscillator frequencies (4.0, 6.4, 8.0 khz with f osc = 64 khz; 16.0, 25.6, 32.0 khz with f osc = 256 khz) master clock frequency (f osc ) 256 khz (rc)/4.096 mhz (ceramic/crystal) 40 khz to 256 khz lpf attenuation factor ?40 db/octave ?24 db/octave lpf cut-off frequency (f cut ), khz maximum phrase number 127 111 pull-up/pull-down resistors built in ? standby conversion time 0.2 sec 3 sec mask options 4 options 14 options added function in phrase control table phrase control table fade-out random playback melody playback pcm playback serial input/port output ? the msm6375 family have already been obsolete devices. we recommend to design with using msm6650 family when you design in your new products. f cut 1.8 2.6 2.6 3.2 4.2 5.1 6.4 12.8 f sam 4.0 5.3 6.4 8.0 10.6 12.8 16.0 32.0 f cut 1.5 3.0 3.0 f sam 4.0 6.4 8.0
fedl6650full-06 oki semiconductor msm6650 family 5/126 standalone mode features maximum playback time (sec) device name rom size f sam = 4.0 khz f sam = 6.4 khz f sam = 8.0 khz f sam = 16 khz msm6652, 6652a 288 kbit s 16.9 10.5 8.4 4.2 msm6653, 6653a 544 kbit s 31.2 19.5 15.6 7.8 msm6654, 6654a 1 mbit 63.8 39.9 31.9 15.9 msm6655, 6655a 1.5 mbit s 96.5 60.3 48.2 24.1 msm6656, 6656a 2 mbit s 129.1 80.7 64.5 32.2 msm6658a 4 mbits 259.7 162.9 129.8 64.9 msm66p56 2 mbit 129.1 80.7 64.5 32.2 msm6650 64 mbits (max) 4194.3 2620.5 2096.4 1048.2 note: actual voice rom area is smaller by 22 kbits. ? 4-bit adpcm or 8-bit pcm sound generation ? melody function ? phrase control table function ? two-channel mixing function ? built-in random playback function ? fade-out function via four-step sound volume attenuation ? built-in beep tone of 0.5 khz, 1.0 khz, 1.3 khz, or 2.0 khz selectable with a specific code ? sampling frequency of 4.0 khz, 5.3 khz, 6.4 khz, 8.0 khz, 10.6 khz, 12.8 khz, 16.0 khz, or 32.0 khz (32 khz sampling is not possible when using rc oscillation) ? up to 120 phrases ? built-in 12-bit d/a converter ? built-in ?40 db/octave low-pass filter ? standby function ? selectable rc or ceramic oscillation ? package options: 18-pin plastic dip (dip18-p-300-2.54) (msm6652-xxxrs/msm6653-xxxrs/ msm6654-xxxrs/msm6655-xxxrs/ msm6656-xxxrs/msm6652a-xxxrs/ msm6653a-xxxrs/msm6654a-xxxrs/ msm6655a-xxxrs/msm6656a-xxxrs/ msm6658a-xxxrs) 24-pin plastic sop (sop24-p-430-1.27-k) (msm6652-xxxgs-k/msm6653-xxxgs-k/ msm6654-xxxgs-k/MSM6655-XXXGS-K/ msm6656-xxxgs-k/msm6652a-xxxgs-k/ msm6653a-xxxgs-k/msm6654a-xxxgs-k/ msm6655a-xxxgs-k/msm6656a-xxxgs-k/ msm6658a-xxxgs-k/msm66p56-03gs-k/ msm66p56-04gs-k) 20-pin plastic dip (dip20-p-300-2.54-w1) (msm66p56-03rs/msm66p56-04rs) 64-pin plastic qfp (qfp64-p-1420-1.00-bk) (msm6650gs-bk)
fedl6650full-06 oki semiconductor msm6650 family 6/126 ? option table microcontroller interf ace mode standalone mode pin name serial input parallel input with standby no standby msm6652/53/54/55/56 msm6652a/53a/54a/ 55a/56a/58a ? mask option msm66p56 ? ?01 ?02 ?03 ?04 cpu ?h? ?h? ?l? ?l? serial ?h? ?l? ?l? ?l? msm6650 stby ? ? ?l? ?h? *1. the options for the mask rom-based devices are mask options. the user should send oki an option list before starting development. a sa mple of option list is shown below. *2. a code of otp version device corresponds to one of the options. the user should specify either msm66p56-03 or msm66p56-04. (in this case, no option list is required.) *1 *2 option input interface mode standby conversion option a option b option c option d microcontroller standalone microcontroller standalone serial parallel ? ? ? ? yes no item ceramic sample mold sample mass produc- tion package (circle the desired one) quantity note 18-pin dip (ceramic) 18-pin dip (plastic) 18-pin dip (plastic) 24-pin sop (ceramic) 24-pin sop (plastic) 24-pin sop (plastic) chip chip chip pcs pcs pcs per lot monthly up to 10 samples. operating temp. : 10 to 30c up to 50 samples option lis t oki electric industry co., ltd. date: you are requested to develop msm665x -xxx on t he following conditions. 1. options there are four options for the msm6650 family. choose and circle the desired option. 2. package and quantity signed by title : company name :
fedl6650full-06 oki semiconductor msm6650 family 7/126 block diagrams msm6652/53/54/55/56-xxx msm6652a/53a/54a/55a/56a/58a-xxx (containing 22 kbit phrase control 16 bit (msm6652/52a) 17 bit (msm6653/53a) 17 bit (msm6654/54a) 18 bit (msm6655/55a) 18 bit (msm6656/56a) 19 bit (msm6658a) multiplexer address & switching controller 7 adpcm synthesizer pcm synthesizer 12 8 12 bit dac lpf aout data controller melody generator beep tone generator 16 bit (msm6652/52a) 17 bit (msm6653/53a) 17 bit (msm6654/54a) 18 bit (msm6655/55a) 18 bit (msm6656/56a) 19 bit (msm6658a) address counter timing controller gnd v dd reset random circuit i/o interface osc ceramic/ crystal/rc xt/ cr a0 a1 a2 sw0 sw1 sw2 sw3 test rnd busy osc1 osc2 osc3 (msm6652/52a) (msm6653/53a) (msm6654/54a) (msm6655/55a) (msm6656/56a) (msm6658a) 288 kbit 544 kbit 1 mbit 1.5 mbit 2 mbit 4 mbit rom table & phrase address table)
fedl6650full-06 oki semiconductor msm6650 family 8/126 msm66p56-xx pgm v pp osc (ceramic/ crystal/rc) 18 bit (msm66p56-xx) multiplexer 18 bit (msm66p56-xx) address counter program circuit 2 mbit otp rom (msm66p56-xx) (containing 22 kbit phrase control table & phrase address table) address & switching controller 7 adpcm synthesizer pcm synthesizer 12 8 12 bit dac lpf aout data controller melody generator beep tone generator timing controller gnd v dd reset random circuit i/o interface xt/ cr a0 a1 a2 sw0 sw2 sw3 test rnd busy osc1 osc2 osc3 sw1
fedl6650full-06 oki semiconductor msm6650 family 9/126 msm6650 8 bit latch 23 bit multiplexer address & switching controller 7 adpcm synthesizer pcm synthesizer 12 8 12 bit dac lpf aout data controller melody generator beep tone generator 23 bit address counter timing controller dgnd dv dd reset random circuit i/o interface osc (ceramic/ crystal/rc) xt/ cr a2 a1 a0 sw3 sw2 sw1 sw0 test1, 3 rnd ce rcs busy nar ibusy standby xt/osc1 xt /osc2 osc3 av dd agnd test2 cpu stby ra22 ra0 d7 d0
fedl6650full-06 oki semiconductor msm6650 family 10/126 pin configuration (top view) the msm66p56-xx has two more pins than the msm6652-6658a while their pin configurations are identical. the additional two pins (v pp , pgm ) of the msm66p56-xx may be open at playback after completion of writing. sm6652-xxxgs-k, msm6653-xxxgs-k, msm6654-xxxgs-k, MSM6655-XXXGS-K, msm66p56-03/-04gs-k msm6656-xxxgs-k, msm6652a-xxxgs-k, msm6653a-xxxgs-k, msm6654a-xxxgs-k, msm6655a-xxxgs-k, msm6656a-xxxgs-k, msm6658a-xxxgs-k msm6652-xxxrs, msm6653-xxxrs, msm6654-xxxrs, msm6655-xxxrs, msm6656-xxxrs, msm6652a-xxxrs, msm66p56-03/-04rs msm6653a-xxxrs, msm6654a-xxxrs, msm6655a-xxxrs, msm6656a-xxxrs, msm6658a-xxxrs 18-pin plastic dip 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 tes t a2 a1 a0 r ese t xt/ cr aout sw3 sw2 sw1 sw0 r nd osc3 osc2 osc1 msm6652-6658a ( mask rom ) 24-pin plastic sop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd osc1 osc2 nc osc3 nc nc rnd sw0 sw1 sw2 sw3 gnd aout xt/ cr nc busy nc nc reset test a2 a1 a0 busy gnd v dd msm6652-6658a ( mask rom ) 20-pin plastic dip 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 tes t a2 a1 a0 v pp rese t busy xt/ c r aout gnd pgm sw3 sw2 sw1 sw0 r nd osc3 osc2 osc1 v dd msm66p56 ( otp ) 24-pin plastic sop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd osc1 osc2 nc osc3 nc pgm rnd sw0 sw1 sw2 sw3 gnd aout xt/ cr nc busy nc v pp reset test a2 a1 a0 msm66p56 ( otp )
fedl6650full-06 oki semiconductor msm6650 family 11/126 msm6650 product name: msm6650gs-bk nc: no connection 64-pin plastic qfp 1 nc busy nar nc aout agnd dgnd av dd dv dd xt/osc1 xt /osc2 osc3 test1 rnd xt/ cr cpu test2 ibusy nc ra10 ra9 ra8 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 d7 d6 d5 d4 d3 d2 d1 nc stby ra22 ra21 ra20 ra19 ra18 ra17 ra16 ra15 ra14 ra13 ra12 ra11 standby sw0 sw1 sw2 sw3 a0 a1 a2 test3 reset ce rcs d0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
fedl6650full-06 oki semiconductor msm6650 family 12/126 pin descriptions 1. msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx 18-pin plastic dip pin symbol type description 5 reset i reset. setting this pin to ?l? puts the lsi in standby status. at this time, oscillation stops, aout is pulled to gnd, and the device is initialized. this pin has an internal pull-up resistor. 6 busy o busy. this pin outputs ?l? level during pl ayback. at power-on, this pin is at ?h? level. 7 xt/ cr i xt/ cr selectable pin. set to ?h? level when using ceramic oscillation. set to ?l? level when using rc oscillation. 8 aout o sound output. this is the synthesized output pin of the internal low-pass filter. 11 osc1 i oscillator 1. this pin is a ceramic osc illator connection pin when using ceramic oscillation. this pin is an rc connection pin when using rc oscillation. when using an external clock, use this pin as the clock input. 12 osc2 o oscillator 2. this pin is a ceramic oscillator connection pin when using a ceramic oscillator. this is an rc connection pin when using rc oscillation. leave open if using an external clock. osc2 outputs ?l? level in standby status. 13 osc3 o oscillator 3. leave open if using a cera mic oscillator. this pin is the rc connection pin when using rc oscillation. when rc oscillation is selected, osc3 outputs ?h? level in standby status. 14 rnd i random playback. random playback starts when the rnd pin is set to ?l? level. at the fall of rnd , addresses from the random address playback circuit inside the ic are fetched. set to ?h? le vel if random playback is not used. this pin has an internal pull-up resistor. 15-18 sw0-sw3 i phrase inputs. these pins are phrase input pins corresponding to playback. if the input changes, sw0 to sw3 pins capture address data after 16 ms and speech playback commences. these pins have internal pull-down resistors. 1-3 a0-a2 i phrase inputs. phrase input pins co rresponding to playback. the a0 input becomes invalid when the random playback function is used. 9 gnd ? ground. 10 v dd ? power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd. 4 test i test mode. set to ?h? level. this pin has an internal pull-up resistor
fedl6650full-06 oki semiconductor msm6650 family 13/126 2. msm66p56-xx 20-pin plastic dip pin symbol type description 6 reset i reset. setting this pin to ?l? puts the lsi in standby status. at this time, oscillation stops, aout is pulled to gnd, and the device is initialized. this pin has an internal pull-up resistor. 7 busy o busy. this pin outputs ?l? level during play back. at power-on, this pin is at ?h? level. 8 xt/ cr i xt/ cr selectable pin. set to ?h? level when using ceramic oscillation. set to ?l? level when using rc oscillation. 9 aout o sound output. this is the synthesized output pin of the internal low-pass filter. 12 osc1 i oscillator 1. this pin is a ceramic osc illator connection pin when using ceramic oscillation. this pin is an rc connection pin when using rc oscillation. when using an external clock, use this pin as the clock input. 13 osc2 o oscillator 2. this pin is a ceramic oscillator connection pin when using a ceramic oscillator. this is an rc connection pin when using rc oscillation. leave open if using an external clock. osc2 outputs ?l? level in standby status. 14 osc3 o oscillator 3. leave open if using a cera mic oscillator. this pin is the rc connection pin when using rc oscillation. when rc oscillation is selected, osc3 outputs ?h? level in standby status. 15 rnd i random playback. random playback starts when the rnd pin is set to ?l? level. at the fall of rnd , addresses from the random address playback circuit inside the ic are fetched. set to ?h? le vel if random playback is not used. this pin has an internal pull-up resistor. 16-19 sw0-sw3 i phrase inputs. these pins are phrase input pins corresponding to playback. if the input changes, sw0 to sw3 pins capture address data after 16 ms and speech playback commences. these pins have internal pull-down resistors. 2-4 a0-a2 i phrase inputs. phrase input pins co rresponding to playback. the a0 input becomes invalid when the random playback function is used. 10 gnd ? ground. 11 v dd ? power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd. 5 test i test mode. set to ?h? level. this pin has an internal pull-up resistor. 1 v pp ? power supply used when writing data to internal otp rom. leave open or set to ?h? level during playback. 20 pgm i interface with voice analysis edit tool ar204. set to ?l? level or leave open during playback.
fedl6650full-06 oki semiconductor msm6650 family 14/126 3. msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx 24-pin plastic sop pin symbol type description 17 reset i reset. setting this pin to ?l? puts the lsi in standby status. at this time, oscillation stops, aout is pulled to gnd, and the device is initialized. this pin has an internal pull-up resistor. 20 busy o busy. this pin outputs ?l? level during play back. at power-on, this pin is at ?h? level. 22 xt/ cr i xt/ cr selectable pin. set to ?h? level when using ceramic oscillation. set to ?l? level when using rc oscillation. 23 aout o sound output. this is the synthesized output pin of the internal low-pass filter. 2 osc1 i oscillator 1. this pin is a ceramic osc illator connection pin when using ceramic oscillation. this pin is an rc connection pin when using rc oscillation. when using an external clock, use this pin as the clock input. 3 osc2 o oscillator 2. this pin is a ceramic oscillator connection pin when using a ceramic oscillator. this is an rc connection pin when using rc oscillation. leave open if using an external clock. osc2 outputs ?l? level in standby status. 5 osc3 o oscillator 3. leave open if using a cera mic oscillator. this pin is the rc connection pin when using rc oscillation. when rc oscillation is selected, osc3 outputs ?h? level in standby status. 8 rnd i random playback. random playback starts when the rnd pin is set to ?l? level. at the fall of rnd , addresses from the random address playback circuit inside the ic are fetched. set to ?h? le vel if random playback is not used. this pin has an internal pull-up resistor. 9-12 sw0-sw3 i phrase inputs. these pins are phrase input pins corresponding to playback. if the input changes, sw0 to sw3 pins capture address data after 16 ms and speech playback commences. these pins have internal pull-down resistors. 13-15 a0-a2 i phrase inputs. phrase input pins co rresponding to playback. the a0 input becomes invalid when the random playback function is used. 24 gnd ? ground. 1 v dd ? power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd. 16 test i test mode. set to ?h? level. this pin has an internal pull-up resistor. 18 v pp * ? power supply used when writing data to internal otp rom. leave pen or set to ?h? level during playback. 7 pgm * i interface with voice analysis edit tool ar204. set to ?l? level or leave open during playback. * pins for msm66p56-xx only
fedl6650full-06 oki semiconductor msm6650 family 15/126 4. msm6650 64-pin plastic qfp pin symbol type description 29 reset i reset. setting this pin to ?l? puts the lsi in standby status. at this time, oscillation stops, aout is pulled to gnd, and the device is initialized. this pin has an internal pull-up resistor. 3 busy o busy. this pin outputs ?l? level during play back. at power-on, this pin is at ?h? level. 15 xt/ cr i xt/ cr selectable pin. set to ?h? level when using ceramic oscillation. set to ?l? level when using rc oscillation. 5 aout o sound output. this is the synthesized output pin of the internal low-pass filter. 10 xt/osc1 i oscillator 1. this pin is a ceramic osc illator connection pin when using ceramic oscillation. this pin is an rc connection pin when using rc oscillation. when using an external clock, use this pin as the clock input. 11 xt /osc2 o oscillator 2. this pin is a ceramic oscillator connection pin when using a ceramic oscillator. this is an rc connection pin when using rc oscillation. leave open if using an external clock. osc2 outputs ?l? level in standby status. 12 osc3 o oscillator 3. leave open if using a cera mic oscillator. this pin is the rc connection pin when using rc oscillation. when rc oscillation is selected, osc3 outputs ?h? level in standby status. 14 rnd i random playback. random playback starts when the rnd pin is set to ?l? level. at the fall of rnd , addresses from the random address playback circuit inside the ic are fetched. set to ?h? le vel if random playback is not used. this pin has an internal pull-up resistor. 21-24 sw0-sw3 i phrase inputs. these pins are phrase input pins corresponding to playback. if the input changes, sw0 to sw3 pins capture address data after 16 ms and speech playback commences. these pins have internal pull-down resistors. 25-27 a0-a2 i phrase inputs. phrase input pins co rresponding to playback. the a0 input becomes invalid when the random playback function is used.
fedl6650full-06 oki semiconductor msm6650 family 16/126 pin symbol type description 6 agnd ? analog ground pin. 7 dgnd ? digital ground pin. 8 av dd ? analog power pin. insert a 0.1 f or more bypass capacitor in between this pin and agnd. 9 dv dd ? digital power pin. insert a 0.1 f or more bypass capacitor in between this pin and dgnd. 16 cpu i cpu mode. set to ?l? level to select st andalone mode. set to ?h? level to select microcontroller interface mode. 13, 28 test1 , 3 i test. set these pins to ?h? level. the test1 and test3 pins have internal pull-up resistor. 17 test2 i test set this pin to ?l? level. 18 ibusy o outputs ?l? level during voice play back (except during standby conversion time), or when the aout pin is at half v dd level. 20 standby o standby indicator. this output pin re mains at ?l? level during oscillation. 30 ce o chip enable. ce is a timing output pin to contro l read of external memory. this pin outputs when rcs is at the ?l? level. th is pin outputs ?h? level when rcs is at the ?h? level. 31 rcs i read chip select. the data bits d0-d7 are internally pulled down when rcs is high. addresses and ce are output when rcs is at ?l? level. the ra22-ra0 address pins become high impedance and ce pin outputs ?h? level when rcs is at the ?h? level. 32 34-40 d0-d7 i external memory data bus. data is input when rcs is low when rcs is high, these pins become low due to in ternal pull-down resistors. 41-63 ra0-ra22 o external memory address. these are address pins for an external memory output when rcs is low. these pins become high impedance status if rcs is in ?h? level. 64 stby i standby control. if set to ?l? leve l, the msm6650 enter s standby mode 0.2 seconds after voice ends. if set to ?h? level, the msm6650 aout output maintains half v dd after voice ends.
fedl6650full-06 oki semiconductor msm6650 family 17/126 absolute maximum ratings (gnd = 0 v) parameter symbol condition rating unit power supply voltage v dd ?0.3 to +7.0 v input voltage v in ta = 25c ?0.3 to v dd + 0.3 v storage temperature t stg ? ?55 to +150 c recommended operating conditions (gnd = 0 v) parameter symbol condition range unit v dd msm6652-56, msm6650, msm6652a-56a 2.4 to 5.5 v power supply voltage v dd msm6658a, msm66p56 3.5 to 5.5 v operating temperature t op ? ?40 to +85 c min. typ. max. master clock frequency 1 f osc1 when crystal selected 3.5 4.096 4.5 mhz master clock frequency 2 f osc2 when rc selected (*) 200 256 300 khz * if rc oscillation is selected, 32 khz sampling frequency cannot be selected.
fedl6650full-06 oki semiconductor msm6650 family 18/126 electrical characteristics dc characteristics (v dd = 5.0 v, gnd = 0 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit ?h? input voltage v ih ? 4.2 ? ? v ?l? input voltage v il ? ? ? 0.8 v ?h? output voltage v oh l oh = ?1 ma 4.6 ? ? v ?l? output voltage v ol l ol = 2 ma ? ? 0.4 v ?h? input current 1 l ih1 v ih = v dd ? ? 10 a ?h? input current 2 l ih2 internal pull-down resistance 30 90 200 a ?l? input current 1 l il1 v il = gnd ?10 ? ? a ?l? input current 2 (note) l il2 internal pull-up resistance ?200 ?90 ?30 a operating power consumption i dd ? ? 6 10 ma ta = ?40c to +50c ? ? 10 a standby power consumption l ds ta = ?40c to +85c ? ? 30 a analog characteristics (v dd = 5.0 v, gnd = 0 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit d/a output relative accuracy |v dae | when d/a output is selected ? ? 40 mv d/a output impedance r dao when d/a output is selected 15 25 35 k ? lpf driving resistance r aout when lpf output is selected 50 ? ? k ? lpf output impedance r lpf i f = 100 a 1 3 k ? 2.0v pp sine wave at 1 khz input waveform, f s = 8 khz, harmonic wave distortion = 2nd-21st harmonic wave component harmonic wave distortion d h signal component + 2nd-21st harmonic wave component ? 2.0 4.0 % noise during silence n s no load, input waveform mute ? 5 20 mv
fedl6650full-06 oki semiconductor msm6650 family 19/126 dc characteristics (v dd = 3.1 v, gnd = 0 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit ?h? input voltage v ih ? 2.7 ? ? v ?l? input voltage v il ? ? ? 0.5 v ?h? output voltage v oh l oh = ?1 ma 2.6 ? ? v ?l? output voltage v ol l ol = 2 ma ? ? 0.4 v ?h? input current 1 l ih1 v ih = v dd ? ? 10 a ?h? input current 2 l ih2 internal pull-down resistance 10 30 100 a ?l? input current 1 l il1 v il = gnd ?10 ? ? a ?l? input current 2 l il2 internal pull-up resistance ?100 ?30 ?10 a operating power consumption i dd ? ? 4 7 ma ta = ?40c to +50c ? ? 5 a standby power consumption l ds ta = ?40c to +85c ? ? 20 a lpf driving resistance r aout when lpf output is selected 50 ? ? k ? lpf output impedance r lpf i f = 100 a ? 1 3 k ? ac characteristics (v dd = 2.4 to 5.5 v, gnd = 0 v, ta = ?40 to +85c) (v dd = 3.5 to 5.5 v, gnd = 0 v, ta = ?40 to +85c) (note) parameter symbol condition min. typ. max. unit master clock duty cycle f duty ? 40 50 60 % reset input pulse width t w( rst ) ? 10 ? ? s reset input time after power-on t d( rst ) ? 0 ? ? s rnd input pulse width t w( ran ) see functional description 5.2 100 ? ? s sw0-sw3 input pulse width t w(sw) ? 16 ? ? ms busy output time 1 t sbs ? ? 10 s busy output time 2 t bn at f sam = 8 khz 130 150 170 s chattering prevention time t cha ? 14 15 16 ms d/a converter change time t dar , t daf ? 60 64 68 ms lpf stable time t l ? 6 8 10 ms standby transition time t stb ? 0.15 0.2 0.25 sec random address capture time t ra see functional description 5.2 16 32 48 s note: applied to msm6658a-xxx and msm66p56-xx.
fedl6650full-06 oki semiconductor msm6650 family 20/126 timing diagrams power-on timing activation of standby state timing when ic is activated * ibusy , standby timings are applied to msm6650 alone. repeated playback timing v dd reset (i) busy (o) t w( rst ) t d( rst ) sw0 (i) busy (o) aout (o) oscillation startup single-phrase playback single-phrase repeated playback t bn d/a converter change time sw0 (i) busy (o) aout (o) t w(sw) oscillation startup t cha standby status ibusy (o) stanby (o) standby status t sbs t l t stb address data ca p ture * * t dar t daf
fedl6650full-06 oki semiconductor msm6650 family 21/126 playback timing during transition of sw0-sw3 repeated random playback timing random address capture timing a2-a0 (i) sw3-sw2 (i) ?l? sw1 (i) sw0 (i) busy (o) aout (o) t cha first phrase play first phrase playback stops second phrase play oscillation startup rnd (i) busy (o) aout (o) oscillation startup first phrase play same phrase repeated play rnd (i) busy (o) aout (o) t w( ran ) t ra oscillation startup voice output random address fixed time
fedl6650full-06 oki semiconductor msm6650 family 22/126 functional description 1. playback code specification the user can specify a maximum of 120 phrases. tabl e 1.1 shows the settings by a2-a0 and sw3-sw0. table 1.1 user specified phrase list a2-a0 sw3-sw0 code description 0000 inhibit code 000 111 0001 1111 user specified phrases (120 phrases) 2. internal rom usage and disabled area (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx) the last 3 bytes of the internal rom are not to be used as shown in table 2.1. please do not use these 3 bytes when creating the sound rom. for example, do not specify other than the msm6652 (such as the msm6653) with development tools ar203 and ar204 when preparing the eprom for the msm6652. table 2.1 shows the addresses that are not to be used for each model. table 2.1 internal rom layout and disabled area type voice data area disabled area msm6652, 6652a 00b00-08ffc 08ffd, 08ffe, 08fff msm6653, 6653a 00b00-10ffc 10ffd, 10ffe, 10fff msm6654, 6654a 00b00-1fffc 1fffd, 1fffe, 1ffff msm6655, 6655a 00b00-2fffc 2fffd, 2fffe, 2ffff msm6656, 6656a 00b00-3fffc 3fffd, 3fffe, 3ffff msm6658a 00b00-7fffc 7fffd, 7fffe, 7ffff msm66p56 00b00-3fffc 3fffd, 3fffe, 3ffff note: addresses are in hex. 3. pull-up/pull-down resistor the reset , rnd and test pins have internal pull-up resistors and the sw3-sw0 pins have internal pull-down resistors. table 3.1 pins with pull-up/pull-down resistor pins with pull-up pins with pull-down msm6652/53/54/55/56 msm6652a/53a/54a /55a/56a/58a reset , rnd , test sw3-sw0 msm66p56 reset , rnd , test sw3-sw0 msm6650 reset , rnd , test1 , 3 sw3-sw0 ? ?
fedl6650full-06 oki semiconductor msm6650 family 23/126 4. option(s) in standalone mode the xt/ cr pin can be used to select the oscillation circ uit. if this pin is set to ?h? level, the circuit is in ceramic oscillation, conversely, if se t to ?l? level, the circuit is in rc oscillation. in the case of rc oscillation, however, a 32 khz sampling frequency cannot be used. an option to move to standby mode can be selected when rewriting rom data. 5. standalone mode in standalone mode, the sw input interface function and the random playback function can be used. 5.1 sw input interface with the sw input interface, voice synthesis starts when sw3-sw0 pins have changed. to prevent chattering, the address is captured 16 ms (t cha ) after sw3-sw0 pins have changed. voice synthesis does not start if a2-a0 pins have changed. set the rnd pin to ?h? level if the random playback function is not used. at power on, sw3-sw0 pins are all ?l? level. the sw input interface is effective when ope rating the msm665x using a push-button switch. speech synthesis starts when an address is changed by pressing the push-button switch. if the push-button switch is released during playback, then playback stops after the current phrase is completed. figure 5.1 sw input interface-playback timing figure 5.1 shows playback timing. sw3-sw0 pins have chattering prevention circuits. the pulse period at each pin requires 16 ms (t cha ) or more. if a push-button switch is continuously pushed, the same phrase is played repeatedly. figure 5.2 shows repeated playback timing. figure 5.3 shows timing when a2-a0 are changed during playback. a2-a0 (i) sw3-sw1 (i) ?l? sw0 (i) busy (o) aout (o) t w(sw) oscillation startup t cha t cha
fedl6650full-06 oki semiconductor msm6650 family 24/126 figure 5.2 sw input interface - repeated playback timing figure 5.3 sw input interface playback timing if sw3-sw0 pins change during playback, then playback stops and the next phrase is played. for the next phrase playback, the voice is first stopped and playback occurs after 16 ms of chattering prevention. figure 5.4 shows timing when sw3-sw0 are changed during playback. playback oscillation startup a2-a0 (i) sw3-sw1 (i) ?l? sw0 (i) busy (o) aout (o) 1st phrase playback 1st phrase continuous a2-a0 (i) sw3-sw1 (i) ?l? sw0 (i) busy (o) aout (o) oscillation startup 1st phrase playback 2nd phrase playback
fedl6650full-06 oki semiconductor msm6650 family 25/126 figure 5.4 timing when sw3-sw0 are changed during playback if playback is attempted at an unused address in the phrase rom, then aout goes to 1/2 v dd and playback does not occur. figure 5.5 shows the timing. figure 5.5 timing when playback is attempted at an unused phrase address in the sw interface, addresses (sw3-sw0 are all ?l?) that do not start up voice playback exist without fail. when power is turned on or when input to reset , the addresses set from sw3 to sw0 become the addresses that do not start up voice playback. theref ore, when the circuit consists of diode ma trixes that use push-button switches, the maximum playback phrases become 120 phrases. combinations of a2-a0 are eight kinds. when addresses of sw3-sw0 that do not start up voice playback are 0000; 2 7 ? 8 = 120 (phrases) a2-a0 (i) sw3-sw2 (i) ?l? sw1 (i) sw0 (i) busy (o) aout (o) t cha 1st phrase playback 1st phrase voice stop 2nd phrase playback oscillation startup a2-a0 (i) sw3-sw1 (i) ?l? sw0 (i) busy (o) aout (o) oscillation startup t bn t l +t dar +t bn
fedl6650full-06 oki semiconductor msm6650 family 26/126 5.2 random playback function the random playback function generates 31 random addresses correspoding to the 5 bits of the addresses of a0, and sw3-sw0 (except all ?l?) on the ic, after which playback commences. this means there is no external input to the a0, sw3-sw 0 pins. since the a0 pin has no internal pull-up/pull- down resistor, permanently set to ?l? or ?h?. playback will not occur if none of the 31 addresses have been assigned a phrase. caution is advised when creating rom data. for example, when four phrases, ?sun ny?, ?rainy?, ?cloudy?, and ?snowy? ar e to be played, set the phrases as shown in table 5.1 to 31 random addresses. the four phrases are then played at random as shown below. table 5.1 random address setup example a2, a1 a0, sw3-sw0 phrase 00001 sunny 00010 rainy 00011 cloudy 00100 snowy 00101 sunny 11110 rainy 00 11111 snowy random playback occurs in accordance with the timing show n in figure 5.6. the random address is captured at the fall of the rnd pin, and voice playback commences. wh en power is turned on, or when reset is input, the phrase at address ?00001? is played while a random counter remains initialized until random playback is initiated. figure 5.6 random address capture ? ? rnd (i) busy (o) aout (o) t w( ran ) t ra oscillation startup voice output random address fixed time
fedl6650full-06 oki semiconductor msm6650 family 27/126 table 5.2 addresses for random play a2, a1 a0, sw3-sw0 * code description 00 00001 11111 random playback address (31 types) 01 10 11 same as above same as above * address(es) corresponding to a0, sw3-sw0 pins. for a random address, 31 phrases can be set for each lo gical condition of addresses a2 and a1 (i.e., ?00?, ?01?, ?10?, and ?11?). in random playback, note that the four logic states (00, 01, 10, 11) in user specified phrases cannot be used when the phrase rom data is prepared. a random address is set by the ?h? level time of the rnd pin, so if the same pulse width is input by microcontroller, the random address fixed time becomes constant, and a ?random? phrase may not be played under these conditions. the random address fixed time must be inconsistent in order to produce random playback. figure 5.7 timing when a pulse is input to the rnd pin during random play ? rnd (i) busy (o) aout (o) oscillation startup invalid pulse
fedl6650full-06 oki semiconductor msm6650 family 28/126 figure 5.8 repeat playback timing of random play as shown in figure 5.7, if a pulse is input to the rnd pin during voice playback ( busy is ?l? level), that pulse becomes invalid. if the rnd pin remains ?l? level after phrase playback has been completed, then the same phrase is repeated, as shown in figure 5.8. if sw3-sw0 are changed during random playback, voice playback stops, and voice data that corresponds to sw3-sw0 is played. figure 5.9 shows the timing when sw3-sw0 are changed during random play. figure 5.9 timing when a pulse is input to the sw0 pin during random playback table 5.3 and figure 5.10 show the address settings that stop random playback. these settings also stop playback when the ?infinite repeat? command is used during phrase control table playback. rnd (i) busy (o) aout (o) oscillation startu p 1st phrase pla y back same phrase continuous pla y back sw3-sw1 (i) sw0 (i) busy (o) aout (o) rnd (i) oscillation startup voice stop playback of random address
fedl6650full-06 oki semiconductor msm6650 family 29/126 table 5.3 random play and stop addresses a2, a1 a0, sw3-sw0 * code description 00 00001 11111 random play address (31 types) 01 00001 stop address * addresses corresponding to a0, sw3-sw0 pins. figure 5.10 circuit exam ple for random play stop 6. sampling frequency sampling frequencies can be speci fied for each phrase in the voice data of the internal rom. for channel synthesis, if channels 1 and 2 are played simultaneously , the channel 1 sampling frequency has priority. when channel 2 is played, only the sampling frequency for the first phrase is valid. the following eight frequencies can be selected when creating voice data. 4.0 khz, 5.3 khz, 6.4 khz, 8.0 khz, 10.6 khz, 12.8 khz, 16.0 khz, 32.0 khz in standalone, rc oscillation or ceramic oscillation can be selected. if rc oscillation is selected however, 32.0 khz sampling cannot be selected. ? sw0 sw1 sw2 sw3 a0 a1 a2 r nd
fedl6650full-06 oki semiconductor msm6650 family 30/126 7. voice playback time table 7.1 shows internal rom configuration. the actual voice data rom area is different from the indicated rom capacity. the voice data management area shown in table 7.1 is a bout 6 kbits, and the phrase control table area includes 16 kbits. table 7.1 rom configuration phrase address data area phrase control table area sound data area test data area use the following formula as a guide to compute voice playback time. playback time = (rom capacity ? 16 ? 6) 1024 255/256 data rate (kbps) for example, if data was created at a 4.0 khz sampling rate using the msm6652 (288-kbit rom), the playback time is (288 ? 16 ? 6) 1024 255/256 16 (kbps) = 16.9 (sec.) 8. channel status the busy pin outputs the status signals. it outputs ?l? level when either channel 1 or 2 is playing voice. ?h? level is output when power is turned on. 9. playback method the msm6375 family uses the adpcm playback method, however the msm6650 family has three playback methods: adpcm, pcm and melody playback. the respective features and selection criteria are explained below. 9.1 adpcm method with the adpcm (adaptive differential pulse-code modulation) method, basic quantization width ? is adaptively changed for each sampling, and is encoded to 4-bit data each time. this further improves the follow-up properties to speech wave forms. conversion to adpcm data is performed by the development tool ar761 or ar762. adpcm is a compression algorithm which provides th e best compromise between quality (bandwidth) and memory usage (data rate). adpcm can be used for accu rate reproduction of voice, music, and sound effects.
fedl6650full-06 oki semiconductor msm6650 family 31/126 9.2 pcm method the pcm method of the msm6650 family uses an 8-bit straight binary format. of the three methods, pcm is best suited to accurate reproduction of sound effects or waveforms which are pulse shaped or change rapidly (such as high frequency pure tone sine-waves). 9.3 melody playback method the ar761 and ar762 development tools support melody regeneration system. the melody data can be composed by using these tools. therefore, unique sound can be created. 9.4 data rate of each method the data rate shows the degree of data compression and the data amount to synthesize for 1 second. the data rate is determined by the relationship between the sampling frequency and the format (number of bits per sample). the following formula is used. data rate (kbps) = sampling frequency (khz) number of bits per sample the data rate of the three methods are compared below when the sampling frequency is 6.4 khz. 1) adpcm method data rate (kbps) = 6.4 (khz) 4 (bit) = 25.6 (kbps) 2) pcm method data rate (kbps) = 6.4 (khz) 8 (bit) = 51.2 (kbps) 3) melody playback method with the melody playback method, the data rate changes depend on the tempo or the kind of note ( ) used. the formula does not determine the data rate changes. the average data rate is 8 kbps. the data rate of the melody playback method is calculated as follows: data rate = number of notes per second data amount per note [kbits] for example, to obtain data rate from the following conditions, f sam = 6.4 khz number of notes per second = 1 time [seconds] taken for each thirty-second note = 0.083 sec (tempo = 90) first, obtain the data amount per note with the following expression: data amount per note [kbits] = data amount per thirty-second note [bits per note] 2 = time taken for each thirty-second note [sec] fsam [hz] 8 [bits] 2 = 0.083 6400 8 2 ? 8.5 [kbits] therefore, when the number of notes per second is 1, the data rate is approximately 8.5 kbps.
fedl6650full-06 oki semiconductor msm6650 family 32/126 9.5 channel synthesis combinations for each playback method melody and beep tone playback is in channel 1 only. table 9.1 channel synthesis combinations voice (adpcm) pcm 0 db ?6 to ?18 db melody 0 db ?6 to ?18 db beep tone silence 0 db * * * * voice (adpcm) ?6 to ?18 db * * 0 db * * * * melody ?6 to ?18 db * * 0 db * * * * pcm ?6 to ?18 db * * beep tone * * silence * in the case of channel synthesis, verify the vo ice quality with the msm6650 evaluation board. the combination of channels 1 and 2 can sometimes cause clipping is either of the channels is recorded at a level that is too high. channel 2 channel 1
fedl6650full-06 oki semiconductor msm6650 family 33/126 10. standby conversion when standby conversion is selected by mask option, if the next phrase does not start within 200 ms after voice ends, the ic enters standby status and all operation stops. if restarted, it takes about 100 ms from the restart to voice start because the ?pop noise? suppr ession circuit is in operation. if standby conversion is not selected by the mask option, the ic does not enter standby status even if voice playback has ceased. current is drawn since aout remains at about 1/2 v dd and oscillation is in opration. if restarted, playback occurs after 350 s. to enter standby status when stan dby conversion is not selected, the reset pulse must be input. if the reset pulse is input, the output level at aout instantaneously goes to gnd level, causing pop noises. table 10.1 standby conversion pin name standby conversion selected no standby conversion selected msm6652/53/54/55/56, msm6652a/53a/54a /55a/56a/58a ? mask option msm66p56 ? ?03 code ?04 code msm6650 stby ?l? ?h? 11. voice output in standalone mode speech is output via an internal lo w-pass filter (lpf). table 11 .1 shows output level of aout pin. this filter consists of switched capacitors. tabl e 11.2 shows the relationship between sampling frequencies and cutoff frequencies. table 11.1 output level of aout pin playback method lowest level center level highest level adpcm approx. 0.15 v dd approx. 0.5 v dd approx. 0.95 v dd pcm approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd melody approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd beep tone approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd
fedl6650full-06 oki semiconductor msm6650 family 34/126 each device of the msm6650 family cont ains a 4-order lpf using the switched capacitor filter technology. the attenuation is ?40 db/oct. the cutoff frequency and lpf frequency change depending on the sampling frequency (f sam ). the cutoff frequency is 0.4 time as low as the sampling frequency. the lpf frequency characteristics at f sam = 8 khz are shown below. table 11.2 cutoff frequencies of low pass filter cutoff frequency sampling frequency (f sam ) msm6650, msm6652a to 6658a (f cut ) msm66p56 (f cut ) 4.0 khz approx. 1.6 khz approx. 1.8 khz 5.3 khz approx. 2.5 khz approx. 2.6 khz 6.4 khz approx. 2.5 khz approx. 2.6 khz 8.0 khz approx. 3.1 khz approx. 3.2 khz 10.6 khz approx. 4.1 khz approx. 4.2 khz 12.8 khz approx. 5.0 khz approx. 5.1 khz 16.0 khz approx. 6.2 khz approx. 6.4 khz 32.0 khz approx. 12.5 khz approx. 12.8 khz note: the cutoff frequency of msm6650 and msm6652a to msm6658a are different from those of msm66p56. figure11.1 lpf frequency characteristics (f sam = 8.0 khz) (applied to msm6650, msm6652a to 58a) figure11.2 lpf frequency characteristics (f sam = 8.0 khz) (applied to msm66p56) 0 ?20 ?40 ?60 [db] 100 1k 10k ?10 10 ?30 ?50 ?80 ?70 20 [hz] 0 ?20 ?40 ?60 [db] 100 1k 10k ?10 10 ?30 ?50 ?80 ?70 20 [hz]
fedl6650full-06 oki semiconductor msm6650 family 35/126 12. low-pass filter pop noise each device of the msm6650 family cont ains a ?pop? noise killer circuit. however, a low-pass filter sel ected may cause ?pop? noise as the filter output's circled portions of the figure 12.1 change by approx. 0.7 v abruptly. figure 12.1 pop noise of low-pass filter ?pop? noise can be reduced by connecting a diode at the aout output (as shown below). figure 12.2 pop noise killer circuit standb y conversion time standb y conve r sion time aout
fedl6650full-06 oki semiconductor msm6650 family 36/126 13. rc oscillation figure 13.1 shows an external circuit diagram using rc oscillation. figure 13.1 rc oscillation 13.1 determining rc constants the rc oscillation frequency characteristics are shown in figures 13.2, 13.3, and 13.4. if f osc is set to 256 khz, refer to the following values to set the c and r2 based on the printed-circuit board type. r1 = 100 k ? , r2 = 30 k ? , c = 30 pf (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx) r1 = 100 k ? , r2 = 25 k ? , c = 20 pf (msm66p56-xx) r1 = 150 k ? , r2 = 45 k ? , c = 10 pf (msm6650) when choosing rc oscillation, the rc oscillation frequency varies according to the fluctuation of the external c and r2. 13.2 fluctuation of rc oscillation frequencies when using a 30 k ? r2, the error due to process variations of the ic is 4% maximum so that the fluctuation of the rc oscillation frequency when using a capacitor (c) of 1% accuracy and a resistor (r 2) of 2% accuracy is a maximum of 7% approximately. osc1 osc2 osc3 r1 r2 c
fedl6650full-06 oki semiconductor msm6650 family 37/126 figure 13.2 rc oscillation frequency characteristics (msm6652/53/54/55/56-xxx, msm6652a /53a/54a/55a/56a/58a-xxx) 10 20 30 40 50 60 70 100 200 300 400 oscillation frequency f osc (khz) load resistance r2 (k ? ) v dd = 3 v r1 = 100 k ? c =20 pf v dd = 5 v r1 = 100 k ? c = 20 pf v dd = 3 v r1 = 100 k ? c = 30 pf v dd = 5 v r1 = 100 k ? c = 30 pf 0
fedl6650full-06 oki semiconductor msm6650 family 38/126 figure 13.3 rc oscillation frequency characteristics (msm66p56) 10 30 40 50 60 70 80 100 200 300 400 oscillation frequency f osc (khz) load resistance r2 (k ? ) v dd = 5.0 v r1 = 100 k ? c = 20 pf v dd = 3.5 v r1 = 100 k ? c = 30 pf v dd = 5.0 v r1 = 100 k ? c = 30 pf v dd = 3.5 v r1 = 100 k ? c = 20 pf 20 0
fedl6650full-06 oki semiconductor msm6650 family 39/126 figure 13.4 rc oscillation frequency characteristics (msm6650) 20 30 40 50 60 70 80 100 200 300 400 oscillation frequency f osc (khz) load resistance r2 (k ? ) v dd = 5 v r1 = 100 k ? c = 10 pf v dd = 5 v r1 = 150 k ? c = 30 pf v dd = 5 v r1 = 100 k ? c = 30 pf v dd = 5 v r1 = 150 k ? c = 10 pf
fedl6650full-06 oki semiconductor msm6650 family 40/126 14. ceramic oscillation figure 14.1 shows an external circuit diagram using a ceramic oscillation. figure 14.1 external circuit diagram figure 14.2 shows an external circuit diagram using a ceramic oscillator, cstls4m09g53-b0 or cstcr4m09g53-r0 made by murata mfg. co., ltd. figure 14.4 shows an extend circuit diagram usi ng a ceramic oscillator, kbr4.0msa/mws/mks/pbrc4.00a made by kyocera corp. when using an oscillator, 4.00 mhz, playback speed is approximately 2% slower than the speed when using the development tools ar204, ar205 and demonstration board. figure 14.2 cstls4m09g53-b0 or cstcr4m09g53-r0 figure 14.4 kbr4.0msa/pbrc4. 00a figure 14.5 kbr4.0mws/mks xt xt c1 c2 xt xt internal capacitor xt xt 33 pf 33 pf xt xt internal capacitor
fedl6650full-06 oki semiconductor msm6650 family 41/126 15. power supply (for msm6650) the msm6650 should be powered from a single power sour ce to the analog section and digital section separately, as shown below. the following power connections are not permitted. +5 v dv dd av dd dgnd agnd msm6650 dv dd av dd analog supply digital supply power supply dv dd av dd
fedl6650full-06 oki semiconductor msm6650 family 42/126 application circuits (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx) application circuit in standalone m ode supporting 15 switch-selected phrases 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sw0 sw1 sw2 sw3 aout v dd xt/ cr test rnd a0 a1 a2 gnd osc3 osc2 osc1 msm6652/53/54/55/56 msm6652a/53a/54a /55a/56a/58a msm66p56
fedl6650full-06 oki semiconductor msm6650 family 43/126 (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx) application circuit in standalone m ode supporting four switch-selected words switches and playback addresses a2 a1 a0 sw3 sw2 sw1 sw0 adr s1 0 0 0 0 0 0 1 01 s2 0 0 0 0 0 1 0 02 s3 0 0 0 0 1 0 0 04 s4 0 0 0 1 0 0 0 08 sw0 aout v dd tes t rnd gnd osc3 osc2 osc1 sw1 sw2 sw3 xt/ c r a0 a1 a2 msm6652/53/54/55/56 msm6652a/53a/54a /55a/56a/58a msm66p56 s4 s3 s2 s1 v dd
fedl6650full-06 oki semiconductor msm6650 family 44/126 (msm6650) application circuit in standalone m ode supporting 15 switch-selected phrases 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sw0 sw1 sw2 sw3 ra15 dv dd xt/ cr test1, 3 rnd a0 a1 a2 dgnd osc3 osc2 osc1 aout ra0 v cc gnd v pp ce a15 a0 d7 o7 d0 o0 ce oe msm6650 msm27c512 av dd agnd
fedl6650full-06 oki semiconductor msm6650 family 45/126 (msm6650) application circuit in standalone mode supporting four 1 mbit eproms sw0 sw1 sw2 sw3 ra18 dv dd xt/ cr test2 rnd a0 a1 a2 dgnd osc3 osc2 osc1 aout ra0 v dd gnd v pp ce a16 a0 d7 o7 d0 o0 oe msm6650 msm27c101 ra17 ra16 ce 2 g 1b 1 g 1y3 1 y2 1 y1 1 y0 1a 74hc139 cpu test3 test1 stby v dd gnd v pp ce a16 a0 o7 o0 oe msm27c101 v dd gnd v pp ce a16 a0 o7 o0 oe msm27c101 v dd gnd v pp ce a16 a0 o7 o0 oe msm27c101 agnd av dd
fedl6650full-06 oki semiconductor msm6650 family 46/126 microcontroller interface mode features maximum playback time (sec) device name data rom size f sam = 4.0 khz f sam = 6.4 khz f sam = 8.0 khz f sam = 16 khz f sam = 32 khz msm6652, 6652a 288 kbits 16.9 10.5 8.4 4.2 2.1 msm6653, 6653a 544 kbits 31.2 19.5 15.6 7.8 3.9 msm6654, 6654a 1 mbit 63.8 39.9 31.9 15.9 7.9 msm6655, 6655a 1.5 mbits 96.5 60.3 48.2 24.1 12.0 msm6656, 6656a 2 mbits 129.1 80.7 64.5 32.2 16.1 msm6658a 4 mbits 259. 7 162.9 129.8 64.9 32.4 msm66p56 2 mbit 129. 1 80.7 64.5 32.2 16.1 msm6650 64 mbits (max) 4194.3 2620.5 2096. 4 1048.2 524.1 note: actual voice rom area is smaller by 22 kbits. ? 4-bit adpcm or 8-bit pcm sound generation ? melody function ? phrase control table function ? two-channel mixing function ? fade-out function via four-step sound volume attenuation ? serial input or parallel input selectable ? built-in beep tone of 0.5 khz, 1.0 khz, 1.3 khz, or 2.0 khz selectable with a specific code ? sampling frequency of 4.0 khz, 5.3 khz, 6.4 khz, 8.0 khz, 10.6 khz, 12.8 khz, 16.0 khz, or 32.0 khz (32 khz sampling is not possible when using rc oscillation) ? up to 127 phrases ? built-in 12-bit d/a converter ? built-in ?40 db/octave low-pass filter ? standby function ? package options: 18-pin plastic dip (dip18-p-300-2.54) (msm6652-xxxrs/msm6653-xxxrs/ msm6654-xxxrs/msm6655-xxxrs/ msm6656-xxxrs/msm6652a-xxxrs/ msm6653a-xxxrs/msm6654a-xxxrs/ msm6655a-xxxrs/msm6656a-xxxrs/ msm6658a-xxxrs) 24-pin plastic sop (sop24-p-430-1.27-k) (msm6652-xxxgs-k/msm6653-xxxgs-k/ msm6654-xxxgs-k/MSM6655-XXXGS-K/ msm6656-xxxgs-k/msm6652a-xxxgs-k/ msm6653a-xxxgs-k/msm6654a-xxxgs-k/ msm6655a-xxxgs-k/msm6656a-xxxgs-k/ msm6658a-xxxgs-k/ msm66p56-01gs-k/ msm66p56-02gs-k) 20-pin plastic dip (dip20-p-300-2.54-w1) (msm66p56-01rs/msm66p56-02rs) 64-pin plastic qfp (qfp64-p-1420-1.00-bk) (msm6650gs-bk)
fedl6650full-06 oki semiconductor msm6650 family 47/126 ? option table microcontroller interf ace mode standalone mode pin name serial input parallel input with standby no standby msm6652/53/54/55/56 msm6652a/53a/54a/ 55a/56a/58a ? mask option msm66p56 ? ?01 ?02 ?03 ?04 cpu ?h? ?h? ?l? ?l? serial ?h? ?l? ?l? ?l? msm6650 stby ? ? ?l? ?h? *1. the options for the mask rom-based devices are mask options. the user should send oki an option list before starting development. a sample of option list is shown below. *2. a code of otp version device corresponds to one of the options. the user should specify either msm66p56-01 or msm66p56-02. (in this case, no option list is required.) *1 *2 option input interface mode standby conversion option a option b option c option d microcontroller standalone microcontroller standalone serial parallel ? ? ? ? yes no item ceramic sample mold sample mass produc- tion package (circle the desired one) quantity note 18-pin dip (ceramic) 18-pin dip (plastic) 18-pin dip (plastic) 24-pin sop (ceramic) 24-pin sop (plastic) 24-pin sop (plastic) chip chip chip pcs pcs pcs per lot monthly up to 10 samples. operating temp. : 10 to 30c up to 50 samples option lis t oki electric industry co., ltd. date: you are requested to develop msm665x -xxx on t he following conditions. 1. options there are four options for the msm6650 family. choose and circle the desired option. 2. package and quantity signed by title : company name :
fedl6650full-06 oki semiconductor msm6650 family 48/126 block diagrams msm6652/53/54/55/56-xxx msm6652a/53a/54a/55a/56a/58a-xxx 19-bit (msm6658a) 18-bit (msm6655/55a) 17-bit (msm6653/53a) 19-bit (msm6658a) 18-bit (msm6655/55a) 17-bit (msm6653/53a) 544-kbit (msm6653/53a) 1.5-mbit (msm6655/55a) 4-mbit (msm6658a) osc multiplexer 16-bit (msm6652/52a) address counter (containing 22-kbit phrase control table & phrase address table) address & command controller 7 adpcm synthesizer pcm synthesizer 12 8 12-bit dac lpf aout data controller melody generator beep tone generator timing controller gnd v dd reset i/o interface xt xt nar busy cmd st ch i0 i1 i2/port0 i3/port1 i4 i6/sd i5/si 17-bit (msm6654/54a) 18-bit (msm6656/56a) 16-bit (msm6652/52a) 17-bit (msm6654/54a) 18-bit (msm6656/56a) 288-kbit (msm6652/52a) 1-mbit (msm6654/54a) 2-mbit (msm6656/56a)
fedl6650full-06 oki semiconductor msm6650 family 49/126 msm66p56-xx pgm v pp osc 18-bit (msm66p56-xx) multiplexer 18-bit (msm66p56-xx) address counter program circuit 2-mbit otp rom (msm66p56-xx) (containing 22-kbit phrase control table & phrase address table) address & command controller 7 adpcm synthesizer pcm synthesizer 12 8 12-bit dac lpf aout data controller melody generator beep tone generator timing controller gnd v dd reset i/o interface xt xt nar busy cmd st ch i0 i1 i2/port0 i3/port1 i4 i5/si i6/sd
fedl6650full-06 oki semiconductor msm6650 family 50/126 msm6650 8-bit latch 23-bit multiplexer address & switching controller 7 adpcm synthesizer pcm synthesizer 12 8 12-bit dac lpf aout data controller melody generator beep tone generator 23-bit address counter timing controller dgnd dv dd reset i/o interface osc test1 i6/sd i5/si i4 i3/port1 i2/port0 i1 i0 ch ce rcs busy nar ibusy standby xt xt mck av dd agnd serial cpu test2 ra22 ra0 d7 d0 st cmd
fedl6650full-06 oki semiconductor msm6650 family 51/126 pin configuration (top view) the msm66p56-xx has two more pins than the msm6652-6658a while their pin configurations are identical. the additional two pins (v pp , pgm ) of the msm66p56-xx may be open at playback after completion of writing. msm6652-xxxrs, msm6653-xxxrs, msm6654-xxxrs, msm6655-xxxrs, msm6656-xxxrs, msm6652a-xxxrs, msm66p56-01/-02rs msm6653a-xxxrs, msm6654a-xxxrs, msm6655a-xxxrs, msm6656a-xxxrs, msm6658a-xxxrs msm6652-xxxgs-k, msm6653-xxxgs-k, msm6654-xxxgs-k, MSM6655-XXXGS-K, msm66p56-01/-02gs-k msm6656-xxxgs-k, msm6652a-xxxgs-k, msm6653a-xxxgs-k, msm6654a-xxxgs-k, msm6655a-xxxgs-k, msm6656a-xxxgs-k, msm6658a-xxxgs-k 18-pin plastic dip 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 c h i6/sd i5/si i4 rese t nar aout i3/port1 i2/port0 i1 i0 st cmd xt xt msm6652-6658a (mask rom) 24-pin plastic sop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd xt xt nc cmd nc nc st i0 i1 i2/port0 i3/port1 gnd aout nar nc b usy nc nc r ese t ch i6/sd i5/si i4 busy gnd v dd msm6652-6658a (mask rom) 20-pin plastic dip 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 c h i6/sd i5/si i4 v pp rese t busy nar aout gnd pgm i3/port1 i2/port0 i1 i0 st c md xt xt v dd msm66p56 (otp) 24-pin plastic sop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd xt xt nc c md nc pgm st i0 i1 i2/port0 i3/port1 gnd aout nar nc b usy nc v pp rese t ch i6/sd i5/si i4 msm66p56 (otp)
fedl6650full-06 oki semiconductor msm6650 family 52/126 msm6650 product name: msm6650gs-bk nc: no connection 64-pin plastic qfp 1 nc busy nar nc aout agnd dgnd av dd dv dd xt xt mck cmd st test 1 cpu serial ibusy nc ra10 ra9 ra8 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 d7 d6 d5 d4 d3 d2 d1 nc test2 ra22 ra21 ra20 ra19 ra18 ra17 ra16 ra15 ra14 ra13 ra12 ra11 standby i0 i1 i2/port0 i3/port1 i4 i5/si i6/sd ch reset ce rcs d0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
fedl6650full-06 oki semiconductor msm6650 family 53/126 pin descriptions 1. msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx 18-pin plastic dip pin symbol type description 5 reset i reset. the devices enter standby status w hen a low level is input to this pin. when reset, oscillation stops the ao ut output goes to ground and the ic status is reinitialize. this pi n has an internal pull-up resistor. 6 busy o busy. outputs ?l? level during playback and ?h? level when power is turned on. 7 nar o the cmd and st inputs become effectiv e when high. nar indicates whether the address bus (10 through 16) is r eady to accept another address. when high, it is ready to accept. nar goes high when power is turned on. 8 aout o analog speech output. d/a converter out put or lpf output is selected by entering the command. 11 xt i ceramic oscillator input. this pin has an internal 0.5 to 5 m ? feedback resistor between xt and xt . if an external clock is used, this is the clock input pin. 12 xt o ceramic oscillator outpu t. if an external clock is used, leave this pin open. 13 cmd i command input and option control. this pin is used as command and option input when cmd is at the high level with st low. if this pin is not used or serial input is optioned, set this pin to ?h? level this pin has an internal pull up resistor. 14 st i start. speech playback star ts at the fall of the st pulse. the 10-16 addresses are latched at the rise of the st pulse. input a st pulse when nar goes to the high level for channels 1 and 2. this pin has an internal pull-up resistor. 4 ch i channel control. channel 1 is selected when the input is pulled high. channel 2 is selected when the input is low. th is pin has an internal pull-up resistor. 3 l6/sd i this pin is command and user-defined phrase input when parallel input is optioned. this pin is serial data (c ommand and address) input when serial input is optioned. 2 i5/si i this pin is command and user-defined phrase input when parallel input is optioned. this pin is used as serial cl ock input when serial input is optioned. 1 i4 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 18 i3/port1 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 17 i2/port0 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 15, 16 i0, i1 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 9 gnd ? ground pin. 10 v dd power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd.
fedl6650full-06 oki semiconductor msm6650 family 54/126 2. msm66p56-xx 20-pin plastic dip pin symbol type description 6 reset i reset. the devices enter standby status w hen a low level is input to this pin. when reset, oscillation stops. the ao ut output goes to ground and the ic status is reinitialized this pin has an internal pull-up resistor. 7 busy o busy. outputs ?l? level during playback and ?h? level when power is turned on. 8 nar o the cmd and st inputs become effectiv e when high. nar indicates whether the address bus (10 through 16) is r eady to accept another address. when high, it is ready to accept. nar goes high when power is turned on. 9 aout o analog speech output. d/a converter out put or lpf output is selected by entering the command. 12 xt i ceramic oscillator input. this pin has an internal 0.5 to 5 m ? feedback resistor between xt and xt . if an external clock is used, this is the clock input pin. 13 xt o ceramic oscillator outpu t. if an external clock is used, leave this pin open. 14 cmd i command input and option control. this pin is used as command and option input when cmd is at the high level with st low. if this pin is not used or serial input is optioned, set this pin to ?h? level. this pin has an internal pull-up resistor. 15 st i start. speech playback star ts at the fall of the st pulse. the 10-16 addresses are latched at the rise of the st pulse. input a st pulse when nar goes to the high level for channels 1 and 2. this pin has an internal pull-up resistor. 5 ch i channel control. channel 1 is selected when the input is pulled high. channel 2 is selected when the input is low. th is pin has an internal pull-up resistor. 4 i6/sd i this pin is command and user-defined phrase input when parallel input is optioned. this pin is serial data (c ommand and address) input when serial input is optioned. 3 i5/si i this pin is command and user-defined phrase input when parallel input is optioned. this pin is used as serial cl ock input when serial input is optioned. 2 i4 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 19 i3/port1 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 18 i2/port0 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion c ode controls the port output. 16, 17 i0, i1 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 10 gnd ? ground pin. 11 v dd ? power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd. 1 v pp ? supply voltage for writing data to internal otp rom. 20 pgm i interface with voice analysis edit tool s ar204. set to ?l? level or leave open during playback. this pin has an internal pull-down resistor.
fedl6650full-06 oki semiconductor msm6650 family 55/126 3. msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx 24-pin plastic sop pin symbol type description 17 reset i reset. the devices enter standby status w hen a low level is input to this pin. when reset, oscillation stops. the ao ut output goes to ground and the ic status is reinitialized this pin has an internal pull-up resistor. 20 busy o busy. outputs ?l? level during playback and ?h? level when power is turned on. 22 nar o the cmd and st inputs become effectiv e when high. nar indicates whether the address bus (10 through 16) is r eady to accept another address. when high, it is ready to accept. nar goes high when power is turned on. 23 aout o analog speech output. d/a converter out put or lpf output is selected by entering the command. 2 xt i ceramic oscillator input. this pin has an internal 0.5 to 5 m ? feedback resistor between xt and xt . if an external clock is used, this is the clock input pin. 3 xt o ceramic oscillator outpu t. if an external clock is used, leave this pin open. 5 cmd i command input and option control. this pin is used as command and option input when cmd is at the high level with st low. if this pin is not used or serial input is optioned, set this pin to ?h? level. this pin has an internal pull-up resistor. 8 st i start. speech playback star ts at the fall of the st pulse. the 10-16 addresses are latched at the rise of the st pulse. input a st pulse when nar goes to the high level for channels 1 and 2. this pin has an internal pull-up resistor. 16 ch i channel control. channel 1 is selected when the input is pulled high. channel 2 is selected when the input is low. th is pin has an internal pull-up resistor. 15 i6/sd i this pin is command and user-defined phrase input when parallel input is optioned. this pin is serial data (c ommand and address) input when serial input is optioned. 14 i5/si i this pin is command and user-defined phrase input when parallel input is optioned. this pin is used as serial cl ock input when serial input is optioned. 13 i4 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 12 i3/port1 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 11 i2/port0 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion c ode controls the port output.
fedl6650full-06 oki semiconductor msm6650 family 56/126 pin symbol type description 9, 10 i0, i1 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 24 gnd ? ground pin. 1 v dd ? power supply. insert a 0.1 f or more bypass capacitor between this pin and gnd. 18 v pp * ? supply voltage for writing data to internal otp rom. 7 pgm * i interface with voice analysis edit tool s ar204. set to ?l? level or leave open during playback. this pin has an internal pull-down resistor. * pins for msm66p56-xx only
fedl6650full-06 oki semiconductor msm6650 family 57/126 4. msm6650 64-pin plastic qfp pin symbol type description 29 reset i reset. the devices enter standby status w hen a low level is input to this pin. when reset, oscillation stops the ao ut output goes to ground and the ic status is reinitialized. this pi n has an internal pull-up resistor. 3 busy o busy. outputs ?l? level during playback and ?h? level when power is turned on. 4 nar o the cmd and st inputs become effectiv e when high. nar indicates whether the address bus (10 through 16) is r eady to accept another address. when high, it is ready to accept. nar goes high when power is turned on. 5 aout o analog speech output. d/a converter out put or lpf output is selected by entering the command. 10 xt i ceramic oscillator input. this pin has an internal 0.5 to 5 m ? feedback resistor between xt and xt . if an external clock is used, this is the clock input pin. 11 xt o ceramic oscillator outpu t. if an external clock is used, leave this pin open. 13 cmd i command input and option control. this pin is used as command and option input when cmd is at the high level with st low. if this pin is not used or serial input is optioned, set this pin to ?h? level this pin has an internal pull up resistor. 14 st i start. speech playback star ts at the fall of the st pulse. the 10-16 addresses are latched at the rise of the st pulse. input a st pulse when nar goes to the high level for channels 1 and 2. this pin has an internal pull-up resistor. 28 ch i channel control. channel 1 is selected when the input is pulled high. channel 2 is selected when the input is low. th is pin has an internal pull-up resistor. 27 l6/sd i this pin is command and user-defined phrase input when parallel input is optioned. this pin is serial data (c ommand and address) input when serial input is optioned. 26 i5/si i this pin is command and user-defined phrase input when parallel input is optioned. this pin is used as serial cl ock input when serial input is optioned. 25 i4 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor. 24 i3/port1 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 23 i2/port0 i/o this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, this pin is a port output. entering external silence insertion code controls the port output. 21, 22 i0, i1 i this pin is command and user-defined phrase input when parallel input is optioned. when serial input is optioned, set this pin to ?l? level. this pin has an internal pull-down resistor.
fedl6650full-06 oki semiconductor msm6650 family 58/126 pin symbol type description 6 agnd ? analog ground pin. 7 dgnd ? digital ground pin. 8 av dd ? analog power pin. insert a 0.1 f or more bypass capacitor between this pin and agnd. 9 dv dd ? digital power pin. insert a 0.1 f or more bypass capacitor between this pin and dgnd. 12 mck o main clock output pin. use mck as a connection pin for the msc1192, etc. when the ic is standby status, mck is held high. 16 cpu i cpu mode. set to ?h? level to select microcontroller interface mode. 17 serial i serial/parallel interface select. this i nput selects either the parallel or the serial input interface. the serial input in terface is selected with a high level; the parallel input interface is selected with a low level. 30 ce o chip enable. ce is a timing output pin to contro l read of external memory. this pin outputs when rcs is at the ?l? level. th is pin outputs ?h? level when rcs is at the ?h? level. 3 rcs i read chip select. the data bits d0-d7 are internally pulled down when rcs is high. addresses and ce are output when rcs is at ?l? level. the ra22-ra0 address pins become high impedance and ce pin outputs ?h? level when rcs is at the ?h? level. 32, 34-40 d0-d7 i external memory data bus. data is input when rcs is low. when rcs is high, these pins become low due to in ternal pull-down resistors. 41-63 ra0-ra22 o external memory address. these are address pins for an external memory output when rcs is low. these pins bec ome high impedance status if rcs is in ?h? level. 15, 64 test1 , 2 i test. set these pins to ?h? level. 18 ibusy o outputs a ?l? level during playba ck or when aout is at 1/2 v dd (except standby conversion) 20 standby o outputs ?l? level during wh ich the device is oscillating.
fedl6650full-06 oki semiconductor msm6650 family 59/126 absolute maximum ratings (gnd = 0 v) parameter symbol condition rating unit power supply voltage v dd ?0.3 to +7.0 v input voltage v in ta = 25c ?0.3 to v dd + 0.3 v storage temperature t stg ? ?55 to +150 c recommended operating conditions (gnd = 0 v) parameter symbol condition range unit msm6652-56, msm6650, msm6652a-56a 2.4 to 5.5 v power supply voltage v dd msm6658a, msm66p56 3.5 to 5.5 v operating temperature t op ? ?40 to +85 c min. typ. max. master clock frequency f osc ? 3.5 4.096 4.5 mhz
fedl6650full-06 oki semiconductor msm6650 family 60/126 electrical characteristics dc characteristics (1) (v dd = 5.0 v, gnd = 0 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit high level input voltage v ih ? 4.2 ? ? v low level input voltage v il ? ? ? 0.8 v high level output voltage v oh l oh = ?1 ma 4.6 ? ? v low level output voltage v ol l ol = 2 ma ? ? 0.4 v high level input current 1 l ih1 v ih = v dd ? ? 10 a high level input current 2 l ih2 internal pull-down resistor 30 90 200 a low level input current 1 l il1 v il = gnd ?10 ? ? a low level input current 2 *1 l il2 internal pull-up resistor ?200 ?90 ?30 a operating current i dd ? ? 6 10 ma ? ? 10 a standby current l ds ta = ?40c to +50c ta = ?40c to +85c ? ? 30 a d/a output relative accuracy |v dae | when d/a output selected ? ? 40 mv when d/a output selected *2 15 25 35 k ? d/a output impedance r dao when d/a output selected *3 15 30 45 k ? lpf driving resistance r aout when lpf output selected 50 ? ? k ? lpf output impedance r lpf l f = 100 a ? 1 3 k ? *1. applied to reset , cmd , st , ch . *2. applied to msm6652/53/54/55/56, ms m6652a/53a/54a/55a /56a/58a, msm6650. *3. applied to msm66p56. dc characteristics (2) (v dd = 3.1 v, gnd = 0 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit high level input voltage v ih ? 2.7 ? ? v low level input voltage v il ? ? ? 0.5 v high level output voltage v oh l oh = ?1 ma 2.6 ? ? v low level output voltage v ol l ol = 2 ma ? ? 0.4 v high level input current 1 l ih1 v ih = v dd ? ? 10 a high level input current 2 l ih2 internal pull-down resistor 10 30 100 a low level input current 1 l il1 v il = gnd ?10 ? ? a low level input current 2 (note) l il2 internal pull-up resistor ?100 ?30 ?10 a operating current i dd ? ? 4 7 ma ? ? 5 a standby current l ds ta = ?40c to +50c ta = ?40c to +85c ? ? 20 a d/a output relative accuracy |v dae | when d/a output selected ? ? 20 mv d/a output impedance r dao when d/a output selected 15 25 35 k ? lpf driving resistance r aout when lpf output selected 50 ? ? k ? lpf output impedance r lpf l f = 100 a ? 1 3 k ? note: applied to reset , cmd , st , ch .
fedl6650full-06 oki semiconductor msm6650 family 61/126 ac characteristics (v dd = 2.4 to 5.5 v, gnd = 0 v, ta = ?40 to +85c) (v dd = 3.5 to 5.5 v, gnd = 0 v, ta = ?40 to +85c) * parameter symbol condition min. typ. max. unit master clock duty cycle f duty ? 40 50 60 % reset input pulse width t w( rst ) ? 10 ? ? s reset input time after power-on t d( rst ) ? 0 ? ? s st input pulse width t ( st ) when using parallel input 0.35 ? 2000 s st - st pulse interval t ss when the stop code is input 40 ? ? s st - st pulse interval t siss during serial input 1 ? ? s data setup time t dw ? 1 ? ? s data hold time t wd ? 1 ? ? s command setup time 1 t csf at power-on 1 ? ? s command setup time 2 t cs ? 1 ? ? s command hold time t sc ? 1 ? ? s channel setup time t chs ? 1 ? ? s channel hold time t sch ? 1 ? ? s serial clock pulse width t w(sck) when using serial input 0.35 ? ? s serial clock setup time t sis ? 1 ? ? s serial clock hold time t ssl ? 1 ? ? s serial data setup time t sds when using serial input 1 ? ? s serial data hold time t ssd when using serial input 1 ? ? s busy output time 1 t sbs ? ? ? 10 s busy output time 2 t bn when f sam = 8 khz 350 375 400 s busy output time 3 t ba when f sam = 8 khz 350 375 400 s nar output time 1 t sns ? ? ? 10 s nar output time 2 t naa when f sam = 8 khz 350 375 400 s nar output time 3 t nab when f sam = 8 khz 350 375 400 s nar output time 4 t nac when f sam = 8 khz 350 375 500 s d/a converter change time t dar , t daf ? 60 64 68 ms lpf stable time t l ? 6 8 10 ms standby conversion time (after voice ends) t stb ? 0.15 0.2 0.25 sec address capture time t ced for msm6650 500 ? ? s * applied to msm6658a-xxx and msm66p56-xx.
fedl6650full-06 oki semiconductor msm6650 family 62/126 timing diagrams power-on timing standby state timing when ic is activated v dd reset (i) busy (o) t w( rst ) t d( rst ) t csf cmd or st (i) busy (o) aout (o) t l t dar t stb t daf t sbs nar (o) t naa st (i) t ( st ) cmd (i) i6-i0 (i) t dw t wd t cs t sc voice playback t sns oscillation startup
fedl6650full-06 oki semiconductor msm6650 family 63/126 channel 1 playback timing with no external commands (parallel input) bus y (o) aout (o) t l t dar nar (o) s t (i) cmd (i) i6-i0 (i) ch (i) t bn t nab t nac ?h? ?h? 1st phrase address 3rd phrase address 1st phrase play 2nd phrase play 3rd phrase play oscillation startup t ba 2nd phrase address
fedl6650full-06 oki semiconductor msm6650 family 64/126 channel 1 playback timing when external commands are used (parallel input) playback timing set by entering an external command remains unchanged unless other external command is entered. therefore, both 1st phrase and 2nd phrase are played in the same timing. to change playback timing, be sure to enter command data before address data. b us y (o) aout (o) nar (o) st (i) cmd (i) i6-i0 (i) ch (i) ?h? command data 1st phrase (address data) 2nd phrase (address data) 1st phrase play 2nd phrase play oscillation startup
fedl6650full-06 oki semiconductor msm6650 family 65/126 channels 1 and 2 playback timing when external commands are used (parallel input) command data keeps a just previous command regardless of the channel. if playback starts without setting of command, the 3rd phrase is played as set in the 2nd phrase. busy (o) aout (o) nar (o) st (i) cmd (i) i6-i0 (i) ch (i) ?h? command data 1st phrase ( address data) command data 2nd phrase (address data) 1st phrase play channel 2 playback 3rd phrase (address data) t sch t chs 2nd phrase play 3rd phrase play oscillation startup
fedl6650full-06 oki semiconductor msm6650 family 66/126 when serial input is selected, data is transferred into the ic when the s t signal is triggere d after serial data is entered. sd is captured on the leading edge of si. note: set i5/si to ?l? level before st falls to ?l? level. busy (o) aout (o) nar (o) st (i) cmd (i) i6/sd (i) ch (i) ?h? i5/si (i) t sds t w( sck ) 1st phrase address serial input 2nd phrase address serial input 1st phrase play ?h? t sis t ssi t sis oscillation startup t sds playback timing with no external commands (serial input)
fedl6650full-06 oki semiconductor msm6650 family 67/126 playback timing with external commands (serial input) serial input enables setting a port output by entering a command. since port output commands and internal commands are shared, if a command for port output is ente r ed, address data should be entered after a command for voice is entered. otherwise, the input is recognized as a silence insertion code by the ic. the number of command inputs are not limited until ad dress input. however, an efective command is the one finall y entered ( common for channel 1 and channel 2 ) . busy (o) aout (o) nar (o) st (i) cmd (i) i6/sd (i) ch (i) ?h? i5/si (i) i3/port1 (o) i2/port0 (o) silence command input command serial input 1st phrase address serial input port output playback command setting ?h? oscillation startup t siss
fedl6650full-06 oki semiconductor msm6650 family 68/126 functional description parallel or serial input can be sel ected for the microcontrolle r interface. table 1.1 sh ows the correspondence, between serial input and parallel input. table 1.1 interface pin name serial input parallel input msm6652/53/54/55/56, msm6652a/53a/54a /55a/56a/58a ? mask option msm66p56 ? ?01 code ?02 code cpu ?h? ?h? msm6650 serial ?h? ?l? 1. playback code specification the user can specify a maximum of 127 phrases. table 1.1 shows the settings by i6 to i0. table 1.2 user specified phrase list i6-i0 code details 00000000 stop code 00000001 11111111 user specified phrase (127 phrases) 2. internal rom usage and disabled area (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xxx) the last 3 bytes of the internal rom are not to be used as shown in table 2.1. please do not use these when creating the sound rom. for example, do not specify other than msm6652 (such as the msm6653) with development tools ar203 and ar204 when preparing the eprom for the msm6652. table 2.1 shows the addresses that are disabled. table 2.1 internal rom layout and disabled area type voice data area disabled area msm6652, 6652a 00b00-08ffc 08ffd, 08ffe, 08fff msm6653, 6653a 00b00-10ffc 10ffd, 10ffe, 10fff msm6654, 6654a 00b00-1fffc 1fffd, 1fffe, 1ffff msm6655, 6655a 00b00-2fffc 2fffd, 2fffe, 2ffff msm6656, 6656a 00b00-3fffc 3fffd, 3fffe, 3ffff msm6658a 00b00-7fffc 7fffd, 7fffe, 7ffff msm66p56 00b00-3fffc 3fffd, 3fffe, 3ffff note: addresses are in hex. ?
fedl6650full-06 oki semiconductor msm6650 family 69/126 3. pull-up/pull-down resistor reset, cmd, st and ch pins have internal pull-up resistor. i6 to i0 pins do not have internal pull-up/pull-down resistor. when serial input option is selected, i4, i1 and i0 pins have internal pull-down resistor. table 3.1 pins with pull-up/pull-down resistor serial input parallel input pull-up resistor pull-down resistor pull-up resistor pull-down resistor msm6652/53/54/55/56, msm 6652a/53a/54a/ 55a/56a/58a reset , cmd , st , ch i4, i1, i0 reset , cmd , st , ch ? msm66p56 reset , cmd , st , ch i4, i1, i0 reset , cmd , st , ch ? msm6650 reset , cmd , st , ch i4, i1, i0 reset , cmd , st , ch ? 4. options in microcontroller interface mode, two op tion selection methods are available; i. e. the mask option to be set at the time of manufacture of rom data and the command option which is set by the command setting. in the mask option, either parallel input or serial input of commands and phrase addresses can be selected. however, when the mask option is selected, no change ca n be made once the option is selected after manufacture of rom data. the command option can select three items. table 4.1 shows selectable options. table 4.1 option item list no item selection remarks 1 standby conversion yes no if standby conversion is selected (yes), the msm665x enters standby unless the next specified phrase is input within 200 ms after voice ends. 2 aout output lpf ou tput dac output 3 maximum amplitude of a single phrase 0 to v dd 1/4v dd to 3/4v dd (1 /2 amplitude) maximum amplitude of a single phrase
fedl6650full-06 oki semiconductor msm6650 family 70/126 an option is set as in table 4.2 when power is turned on. table 4.2 option selection when power is turned on and at reset input standby conversion aout out put amplitude for 1 phrase yes lpf output 0 to v dd to change an option that is already set, use the command input. if the reset pin is set to ?l? level, the option returns to the status when pow er was turned on (table 4.2). after setting the option, be certain to input the voice, silence and beep tone commands, then start up. figures 4.1 and 4.2 show the option set timing, a nd tables 4.3 and 4.4 show the corresponding options. figure 4.1 option set timing (during parallel input) table 4.3 relationship between options and i3, i2, i0 i3 i2 i0 aout standby conversion amplitude of a single phrase ?0? data lpf yes 0 to v dd ?1? data dac no 1/4 v dd to 3/4 v dd i6/sd (i) ?l? i5/si (i) ?l? i3, i2, i0 (i) cmd (i) st (i) option set data option data capture
fedl6650full-06 oki semiconductor msm6650 family 71/126 figure 4.2 option set timing (during serial input) table 4.4 relationship between options and serial data aout standby conversion amplitude of a single phrase ?0? data lpf yes 0 to v dd ?1? data dac no 1/4 v dd to 3/4 v dd i6/sd (i) i5/si (i) st (i) aout standby conversion amplitude of 1 phrase option data capture
fedl6650full-06 oki semiconductor msm6650 family 72/126 5. microcontroller interface mode external command settings are enabled with the microcontro ller interface. however, if th e phrase control table is used, the command settings of channel 1 are disabled. figures 5.1 and 5.2 show the command input and address input method when using the microcontroller interface. figure 5.1 command, address input timing (parallel input) figure 5.2 command, address input timing (serial input) i6-i0 (i) cmd (i) st (i) busy (o) nar (o) aout (o) command data address data oscillation startup voice end busy (o) aout (o) nar (o) st (i) i6/sd (i) i5/si (i) i6 i5 i4 i3 i2 i1 i0 i6 i5 i4 i3 i2 i1 i0 command input address input oscillation startup t siss
fedl6650full-06 oki semiconductor msm6650 family 73/126 in microcontroller interface serial input , command and address data are identifie d by the initial data input serially. if the initial data is ?h? level, it is identified as command data, if ?l?, it is identified as address data. command and address data must be input after the comm and and address identification data are input initially. figures 5.3, 5.4 and 5.5 show the external input flow. figure 5.3 input flowchart when command is not set power on address input voice ended? end no yes nar is ?h?? st pulse input no yes
fedl6650full-06 oki semiconductor msm6650 family 74/126 figure 5.4 parallel input flowchart when external command is used power on option code set set ch pin to ?h? yes option set ? no yes channel set ? set ch pin to ?l? set cmd pin to ?l? command is set ? nar is ?h? ? 1. voice 2. beep tone 3. silence beep tone set 1. frequency set 2. sound volume set silence insertion code set ( port output set) voice control code set 1. smoothing set 2. repeat set 3. sound volume set st pulse input set cmd pin to ?h? st pulse input set cmd pin to ?h? silence time set beep tone time set phrase address input st pulse input ended ? end no yes a ddress data input command data input (*) 2 1 3 no no 2ch 1ch yes st pulse input set cmd pin to ?h? *beep tone code cannot be set for channel 2.
fedl6650full-06 oki semiconductor msm6650 family 75/126 figure 5.5 serial input flowchart when external command is used end phrase address input beep tone time set silence time set pulse input to i5 pulse input to i5 pulse input to i5 set i6 pin to ?l? set i6 pin to ?l? set i6 pin to ?l? set st pin to ?l? set st pin to ?l? set st pin to ?l? set st pin to ?h? set st pin to ?h? set st pin to ?h? ended ? nar is ?h? ? option set ? command set ? set ch pin to ?l? set ch pin to ?h? channel set ? set st pin to ?h? option code set pulse input to i5 set i6 pin to ?l? set st pin to ?l? power on no yes 1. voice 2. beep tone 3. silence beep tone code set 1. frequency set 2. sound volume set silence insertion code set (port output set) voice control code set 1. smoothing set 2. repeat set 3. sound volume set no yes no no 2ch 1ch * beep tone code cannot be set for channel 2. pulse input to i5 set i6 pin to ?h? set st pin to ?l? yes yes 31 2 (*)
fedl6650full-06 oki semiconductor msm6650 family 76/126 6. command data table 6.1 shows the conditions that can be set by the command data. command data is set with i6-i0. in serial input, data is input corresponding to i6-i0 serially as shown in figure 5.2. table 6.1 command setting content list i6 i5 i4 i3 i2 i1 i0 command description 0 0 0 0a 0s 0 0v option setting three options can be set. the ?0? data option is set upon power on or after reset input. (see table 4.2.) 0 1 0 p1 p0 0 0 silence insertion code the silence insertion code insert s silence into the specified channel. it also sets the port output signals by using the i2 and i3 pins when serial input is selected. after the silence insertion code is input, the silence time is set by address data in put. silence time = address data (i6 to i0) 16.384 ms 1 0 0 bl1 bl0 bf1 bf0 beep tone code after the beep tone code is input, entering address data sets the beep tone time. beep tone time = address data (i6 to i0) 16.384 ms 1 1 sm rp 1 rp0 vl1 vl0 voice control code the voice control code se ts the number of repeats and sound volume. when the number of repeats is set, sound volume smoothing can also be set. pin i3 (oa) i2 (os) i0 (ov) option item aout output standby conversion amplitude of a single phrase ?0? data lpf yes 0 to v dd ?1? data dac no 1/4v dd to 3/4v dd i3 (bl1) i2 (bl0) volume 0 0 1/8 amplitude of channel 1 0 1 1/4 amplitude of channel 1 1 0 1/3 amplitude of channel 1 1 1 1/2 amplitude of channel 1 l1 (bf1) l0 (bf0) frequency (khz) 0 0 0.5 0 1 1.0 1 0 1.3 1 1 2.0 i4 (sm) volume smoothing during repeating 0 disabled 1 enabled i3 (rp1) i2 (rp0) number of repeats 0 0 1 0 1 2 1 0 4 1 1 infinite i1 (vl1) i0 (vo0) attenuation 0 0 0 db 0 1 ?6 db 1 0 ?12 db 1 1 ?18 db
fedl6650full-06 oki semiconductor msm6650 family 77/126 6.1 option code setting an option can be set by command after power on. once an option is set, it remains effective until either power is shut off or until the reset signal is input. when an option is set, input speech, silence and beep tone commands again by command and address data input (phrase, silence time and beep tone time). table 6.2 shows the options that can be set. table 6.2 relationship between options and i3, i2, i0 i3 i2 i0 aout standby conversion amplitude of a single phrase ?0? data lpf yes 0 to v dd ?1? data dac no 1/4 v dd to 3/4 v dd see figure 4.2 for command option set timing chart. options can be set anytime, but if set during playback, the output impedance and amplitude of aout may change.
fedl6650full-06 oki semiconductor msm6650 family 78/126 6.2 silence insertion code silence insertion code inserts silence in the specified channel externally, thereb y reducing voice data. it also sets the port output signals when serial input is selected. i6 i5 i4 i3 i2 i1 i0 0 1 x p1 p0 x x x: don?t care silence is inserted with command data, and silence time is set with address data. the ch pin selects the channel for silence insertion (channel 1 or 2). silence time is set by address data (i6 to i0). minimum silence time: 16.384 ms maximum silence time: (128 ? 1) 16.384 ms = 2.1 sec figure 6.1 shows the channel 1 silence insertion set timing. figure 6.1 channel 1 silence set timing (parallel input) i6/sd (i) i5/si (i) i4-i0 (i) ch (i) cmd (i) st (i) busy (o) nar (o) aout (o) ?h? don't care silence time setting data silence time setting data silence time setting data silence command capture silence time capture silence time (t mu )
fedl6650full-06 oki semiconductor msm6650 family 79/126 for example, if silence time set data shown in figure 6. 1 is set to (i6 to i0) = (? 0011000?), the silence time (t mu ) becomes (2 6 0 + 2 5 0 + 2 4 1 + 2 3 1 + 2 2 0 + 2 1 0 + 2 0 0) 16.384 ms = 393.216 ms the formula to set silence time is shown below. t mu = (2 6 (i6) + 2 5 (i5) + 2 4 (i4) + 2 3 (i3) + 2 2 (i2) + 2 1 (i1) + 2 0 (i0)) 16.384 ms the channel 2 silence insertion set timing is as shown in figure 6.2. figure 6.2 channel 2 silence set timing (parallel input) in serial input, the port output signals from i3/port1, i2 /port0 are also controlled by the silence insertion code. i3/port1, i2/port0 are in ?l? level wh en power is turned on, and when the reset signal is input. when setting the port outputs, first set the port output with a silence insertion code, then input a voice playback code and set the address. figure 6.3 shows the timing. a port cannot be set continuously, if it is necessary to set a port again (after previously being set) a beep tone or voice playback code must first be input, after which the port can be set again. i6/sd (i) i5/si (i) i4-i0 (i) ch (i) cmd (i) st (i) busy (o) nar (o) aout (o) don't care silence time setting data silence time setting data silence time setting data silence command capture silence time capture silence time (t mu )
fedl6650full-06 oki semiconductor msm6650 family 80/126 figure 6.3 port output and command, address set timing (during serial input) busy (o) aout (o) nar (o) st (i) cmd (i) i6/sd (i) ch (i) ?h? i5/si (i) i3/port1 (o) i2/port0 (o) ?h? command (silence insertion) input command (voice control) input address input port output voice playback code set oscillation startup t siss
fedl6650full-06 oki semiconductor msm6650 family 81/126 6.3 beep tone code the beep tone code produces the tone from an internal circuit which is independent of the adpcm circuitry. a beep tone can be set in channel 1 only. when mixing a beep tone (channel 1) and an 8 khz phrase in channel 2, be advised that playback of the phrase (at 8 khz), also plays the beep tone at the phrase frequency (8 khz). i6 i5 i4 i3 i2 i1 i0 1 0 0 bl1 bl0 bf1 bf0 the sound volume is set with i3, i2 pins, and the frequency is set with i1, i0 pins. tables 6.3 and 6.4 show the sound volumes and the frequencies that can be set. i3 i2 sound volume (note 1) i1 i0 frequency 0 0 1/8 amplitude sound volume of channel 1 0 0 0.5 khz 0 1 1/4 amplitude sound volume of channel 1 0 1 1.0 khz 1 0 1/3 amplitude sound volume of channel 1 1 0 1.3 khz 1 1 1/2 amplitude sound volume of channel 1 1 1 2.0 khz note1. if 1/2 amplitude of channel 1 is set, and if the maximum amplitude is set to 1/2 v dd as an option the sound volume of the beep tone becomes 1/4 v dd . the beep tone time is set by address data (i6 to i0). minmum beep tone time: 16.384 ms maximum beep tone time: (128 ? 1) 16.384 ms = 2.1 sec. (approx.) table 6.3 sound volume settings table 6.4 frequency settings
fedl6650full-06 oki semiconductor msm6650 family 82/126 figure 6.4 shows beep tone set timing. figure 6.4 beep set timing (during parallel input) for example, if the beep tone time set data shown in figur e 6.4 is set as (i6 to i0) = (?0011000?), the beep tone time (t be ) is (2 6 0 + 2 5 0 + 2 4 1 + 2 3 1 + 2 2 0 + 2 1 0 + 2 0 0) 16.384 ms = 393.216 ms the formula to set beep tone time is shown below. t be = (2 6 (i6) + 2 5 (i5) + 2 4 (i4) + 2 3 (i3) + 2 2 (i2) + 2 1 (i1) + 2 0 (i0)) 16.384 ms 6.4 voice control code command data can set the number of repeats and sound volume. i6 i5 i4 i3 i2 i1 i0 1 1 sm rp1 rp0 vl1 vl0 i6/sd (i) i5/si (i) i4-i0 (i) ch (i) cmd (i) st (i) busy (o) nar (o) aout (o) sound volume frequency setting beep tone time set data beep tone time set data beep tone time set data beep tone command capture beep tone time capture beep tone time (t be ) ?h?
fedl6650full-06 oki semiconductor msm6650 family 83/126 channel 1 is set when the ch pin is ?h? level, channel 2 is set when ch is ?l? level. once a command is set, it is maintained as both channels until anothe r command is input. the c ondition of each channel is set by i4 to i0. three conditions can be set: 1) to 3). 1) setting the number of repeats the number of repeats is set by the i3 and i2 pins, and four types can be selected: 1, 2, 4 and infinite. a stop code must be input to stop voice when infinite repeat is selected. table 6.5 shows the relationship between i3 and i2 pins, and the number of repeats. table 6.5 selection of number of repeats i3 i2 number of repeats 0 0 1 0 1 2 1 0 4 1 1 infinite 2) sound volume smoothing during repeat if ?i4? is set to a ?1?, sound volume during repeat is automatically attenuated from 1 to 1/2, 1/4 and 1/8 (fade-out function). this smoothing, however, is effective only when 2, 4 or infinite is selected for the repeat setting. if infinite is selected, voice is played, remaining at 1/8 sound volume after attenuating from 1, 1/2, 1/4 and to 1/8. if the initial sound volume setting is other than 1, the sound volume attenuates from that value in 1/2 units, stopping at 1/8. 3) setting sound volume voice volume can be changed in four steps if voice is played overlapping in channel synthesis. the sound volume is set at i1 and i0 pins. table 6.6 shows the relationship between i1, i0 pins and sound volume settings. table 6.6 volume attenuation setting i1 l0 volume attenuation 0 0 no attenuation (sound volume is same as voice data) 0 1 ?6 db attenuation (sound volu me is 1/2 of voice data) 1 0 ?12 db attenuation (sound volu me is 1/4 of voice data) 1 1 ?18 db attenuation (sound volu me is 1/8 of voice data)
fedl6650full-06 oki semiconductor msm6650 family 84/126 7. address data if a phrase is input at i6 to i0 by address data, and if st pulse is then applied, voice playback starts. figure 7.1 shows voice start timing. figure 7.2 and 7.3 show timing when an address, other than a phrase, is input. figure 7.1 voice startup timing figure 7.2 timing when address, other than a phrase, is input in standby status i6-i0 (i) cmd (i) st (i) busy (o) nar (o) aout (o) invalid p hrase address ?h? oscillation startu p i6-i0 (i) cmd (i) st (i) busy (o) nar (o) aout (o) user phrase oscillation startup voice end ?h?
fedl6650full-06 oki semiconductor msm6650 family 85/126 figure 7.3 timing when address, other than a phrase, is input when aout is 1/2 v dd 8. stop code when i6 to i0 are set to ?0000000? during voice playback and a st signal is input, playback stops and aout becomes 1/2 v dd . stop code becomes valid at the leading edge of st (common to parallel and serial inputs). use the stop code only when the busy pin is ?l? level. the stop code cannot be used in states of standby mode. note: 1. if the stop code is input while busy is at th e ?h? level or in standby state (i.e. when aout is gnd), busy goes to the ?l? level for approximately 400 ms. 2. if the next data is input within 80 ms after the st op code is input while busy is at the ?h? level or in standby state (i.e. when aout is gnd), busy and nar are kept in "l" state and do not return to ?h?. 3. if the next data is input within 40 s after the stop code is input while voice is being played, nar is kept in ?l? state and does not return to ?h?. 4. when the phrase address is input during a standby mode and the stop code is input during standby transition, nar cannot go back to ?h?. figure 8.1 indicates the timing. parameter symbol condition min. unit stop input time t bss during pop noise occurrence 80 ms figure 8.1 stop code input timing i6-i0 (i) cmd (i) st (i) busy (o) nar (o) aout (o) invalid phrase address ?h? ?h? 1/2 v dd i6-i0 st aout user phrase or silence code ?0000000? t bss
fedl6650full-06 oki semiconductor msm6650 family 86/126 figure 8.2 shows stop code input timing. note: t ss is also applied for serial input. figure 8.2 stop code input timing (at parallel input) the stop code is a function not to initialize the internal, bu t to stop a voice. to initialize the internal register, use the reset pin. figure 8.3 stop code input timing (at serial input) i6-i0 (i) cmd (i) st (i) busy (o) nar (o) aout (o) user phrase ?0000000? ?h? voice stop t ss (note) 1/2 v dd busy (o) aout (o) nar (o) st (i) i6/sd (i) i5/si (i) t ss user phrase voice stop
fedl6650full-06 oki semiconductor msm6650 family 87/126 conventionally, the stop code input is to externally specify 00h as address data. in order to shorten the specified time t ss , the stop code input also is to internally specify 00h as command data as shown below. however, the stop code must be input while the busy output is active. notes: 1) the stop code input method is determined depending on whether serial input or parallel input is selected. 2) your selected command option is subject to change by initialization when the power is turned on after the stop code is input. therefore, it is n ecessary to select the command option again. 3) the processing after input of the stop code differs depending on whether phrase control table is used or not. the following are basic input timings, and input timings when the selected command option is changed, in serial input mode and in parallel input mode.
fedl6650full-06 oki semiconductor msm6650 family 88/126 inputting the stop code using cmd pin 1. basic input timings (1) when serial input is selected (option a, msm66p56-01, msm6650) input condition: when busy is ?l? (2) when parallel input is selected (option b, msm66p56-02, msm6650) input condition: when busy is ?l? differences between the command stop and conventional stop (1) serial input (2) parallel input command stop conventional stop command stop conventional stop command re-input immediately after input of stop code necessary unnecessary necessary unnecessary t ss ( s) 1 (min.) 40 (min.) 1 (min.) 40 (min.) i6/sd busy st i5/si t ss = 1 s (min) stop code input by command voice control code input voice stop st busy cmd 16 to i0 t ss = 1 s (min) stop code input by command voice control code input voice stop
fedl6650full-06 oki semiconductor msm6650 family 89/126 2. input timings when the selected command option is changed (1) when serial input is selected (option a, msm66p56-01, msm6650) input condition: when busy is ?l? (2) when parallel input is selected (option b, msm66p56-02, msm6650) input condition: when busy is ?l? i6/sd busy st i5/si t ss = 1 s (min) voice stop stop code input by command voice control code input re-select option phrase address input st busy cmd i6 to i0 t ss = 1 s (min) stop code voice stop re-select option phrase address input voice control code
fedl6650full-06 oki semiconductor msm6650 family 90/126 9. sampling frequency sampling frequencies can be selected for each phrase ad dress of the internal rom. for channel mixing, when channels 1 and 2 are played back at the same time, the channel 1 sampling frequency has priority. when channel 2 is played back by itself (channel 1 is not used) it can be played at a sampling frequency different from channel 1 but only for the first phrase played back by channel 2. after the first phrase playback of channel 2 the second (and all other) phrases will be play ed back at the channel 1 sample rate. the following 8 frequencies can be selected when creating voice data. 4.0 khz, 5.3 khz, 6.4 khz, 8.0 khz, 10.6 khz, 12.8 khz, 16.0 khz, 32.0 khz 10. voice playback time table 10.1 shows the internal rom co nfiguration. the actual voice data rom area is different from the indicated rom capacity. the voice data management area as shown in table 10.1 is about 6 kbits, and the phrase control table area includes 16 kbits. table 10.1 rom configuration phrase address data area phrase control table area sound data area test data area use the following formula as a guide to compute voice playback time. playback time = (rom capacity ? 16 ?6 ) 1024 255/256 data rate (kbps) for example, if data was created at a 4.0 khz sampli ng using msm6652 (288-kbit internal rom), the playback time is (288 ? 16 ?6) 1024 255/256 16 (kbps) = 16.9 (sec.)
fedl6650full-06 oki semiconductor msm6650 family 91/126 11. channel status the busy and nar pins output status signals. the busy and nar pins output status signals. the busy pin outputs a ?h? level when the power is turned on and a ?l? level when either channel 1 or channel 2 is playing. the nar (next address request) pin outputs the channel 1 and 2 input status. the ch pin allows the user to see the status of channel 1 and 2 (not channel 1 or channel 2) regardless of the ch pin logic level. this is because both ch annels are logically anded so their status cannot be determined independently through use of the ch pin. consequently, if the nar status of channel 1 is read using the ch pin after playback has been completed, the status level of channel 2 cannot be accurately determined (e.g., ?h? or ?l?). the nar pin outputs the channel 1 and 2 input status signal (next address request). when this pin is at the ?h? level, the st pulse can be input. the cha nnel status is switched by the ch pin. if the ch pin is at the ?h? level, the status signal of channel 1 is output, and if ch is ?l? level, the status of channel 2 is output. 12. playback method the msm6650 has 3 playback methods: adpcm, pcm and melody play. 12.1 adpcm method with the adpcm (adaptive differential pulse code modulation) method, basic quantization width ? is adaptively changed for each sampling, and is encoded to 4-bit data. conversion to adpcm data can be accomplishe d by the ar761 or ar 762 development tool. the adpcm method is used for voice, music, and sound effects. it is considered the best compromise between high quality reproduction and memory usage. 12.2 pcm method the pcm method of the msm6650 uses an 8-bit straight binary format. of the three methods, pcm is the best suited for accurate reproduction of sound effects or waveforms which are pulse shaped or change rapidly (such as high frequency pure tone sine waves). 12.3 melody playback method composed by using these tools. therefore, unique sound can be created.
fedl6650full-06 oki semiconductor msm6650 family 92/126 12.4 data rate of each method the data rate shows the degree of data compression and the data amount to synthesize for 1 second. the data rate is determined by the relationship between the sampling frequency and the data format (in number of bits per sample). the following formula is used. data rate (kbps) = sampling frequency (khz) data format (in number of bits per sample) the data rate of the three methods are compared below when the sampling frequency is 6.4 khz. 1) adpcm method data rate (kbps) = 6.4 (khz) 4 (bits) = 25.6 (kbps) 2) pcm method data rate (kbps) = 6.4 (khz) 8 (bits) = 51.2 (kbps) 3) melody playback method with the melody playback method, the data rate changes depend on the tempo or the kind of note ( ) used. the formula does not determine the data rate changes. the average data rate is 8 kbps. the data rate of the melody playback method is calculated as follows: data rate = number of notes per second data amount per note [kbits] for example, to obtain data rate from the following conditions, f s = 6.4 khz number of notes per second = 1 time [seconds] taken for each thirty-second note = 0.083 sec (tempo = 90) first, obtain the data amount per note with the following expression: data amount per note [kbits] = data amount per thirty-second note [bits per note] 2 ? time taken for each thirty-second note [sec] f s [hz] 8 [bits] 2 = 0.083 6400 8 2 8.5 [kbits] therefore, when the number of notes per second is 1, the data rate is approximately 8.5 kbps.
fedl6650full-06 oki semiconductor msm6650 family 93/126 12.5 channel synthesis combinations for each playback method melody and beep tone playback is in channel 1 only. table 12.1 channel synthesis combinations voice (adpcm) pcm 0 db ?6 to ?18 db melody 0 db ?6 to ?18 db beep tone silence 0 db * * * * voice (adpcm) ?6 to ?18 db * * 0 db * * * * melody ?6 to ?18 db * * 0 db * * * * pcm ?6 to ?18 db * * beep tone * * silence * in the case of channel synthesis, verify the vo ice quality with the msm6650 evaluation board. the combination of channel 1 and 2 can sometimes cause ch ipping if either of t he channels is recorded at a level that is too high. channel 2 channel 1
fedl6650full-06 oki semiconductor msm6650 family 94/126 13. standby conversion if standby conversion yes is selected by command option, th e ic enters standby status and stops all operations if the next phrase does not start up within 0.2 sec after playback ends. if restarted it takes about 100 ms until voice starts, since a pop noise countermeasure circuit operates. if standby conversion no is selected by command option, the ic does not enter standby status, even if voice ends, and the output of aout becomes about 1/2 v dd . current is flowing since oscillati on is operating. if started up voice starts in about 350 ms. if standby conversion no is selected, it is necessary to input a reset pulse to enter standby status. if a reset pulse is input, a pop noise is generated since the aout output level instantaneously becomes gnd level. figure 13.1 st pulse input timing during standby conversion as shown in figure 13.1, when st pulse is input during standby conversion after voice ends, the ic exits from standby status, and the output of aout goes 1/2 v dd . when the output reaches 1/2 v dd , voice synthesis starts. 14. voice output for the voice output pin, a command option can select whether the da converter output is directly output or output through an internal low-pass filter. table 14.1 shows output level of aout pin. table 14.1 output level of aout pin regeneration method condition lowest level center level highest level da converter output 0 approx. 0.5 v dd approx. v dd adpcm lpf output approx. 0.15 v dd approx. 0.5 v dd approx. 0.95 v dd pcm ? approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd melody ? approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd beep tone ? approx. 0.25 v dd approx. 0.5 v dd approx. 0.75 v dd busy aout nar st cmd i6-i0 ?h?
fedl6650full-06 oki semiconductor msm6650 family 95/126 14.1 d/a converter output wave form the output amplitude from the d/a converter becomes a step wave form synchronizing the sampling frequency at a maximum 4095/4096 v dd . if d/a output is selected, it is recommended to externally attach a low-pass filter. since the output impedance of a d/a converter changes between 15 k ? to 35 k ? , determine the filter constant so that this resistance change does not affect the cutoff frequency of the low-pass filter. 14.2 low-pass filter output the low-pass filter consists of switched capacitors. the attenuation characteristic of the msm6650 family device low-pass filter is ?40 db/oct. the cutoff frequency changes depending on the sampling frequency. the cutoff frequency is 0.4 time as low as the sampling frequency. table 14.2 shows the relationship between sampling frequency and cutoff frequency. table 14.2 cutoff frequencies of low-pass filter cutoff frequency sampling frequency (f sam ) (khz) msm6650 msm6652a to 6658a (f cut ) msm66p56 (f cut ) 4.0 approx. 1.6 khz approx. 1.8 khz 5.3 approx. 2.5 khz approx. 2.6 khz 6.4 approx. 2.5 khz approx. 2.6 khz 8.0 approx. 3.1 khz approx. 3.2 khz 10.6 approx. 4.1 khz approx. 4.2 khz 12.8 approx. 5.0 khz approx. 5.1 khz 16.0 approx. 6.2 khz approx. 6.4 khz 32.0 approx. 12.5 khz approx. 12.8 khz figure14.1 lpf frequency characteristics (f sam = 8.0 khz) ( applied to msm6650, msm6652a to 58a ) figure14.2 lpf frequency characteristics (f sam = 8.0 khz) ( applied to msm66p56 ) 0 ?20 ?40 ?60 [db] 100 1k 10k ?10 10 ?30 ?50 ?80 ?70 20 [hz] 0 ?20 ?40 ?60 [db] 100 1k 10k ?10 10 ?30 ?50 ?80 ?70 20 [hz]
fedl6650full-06 oki semiconductor msm6650 family 96/126 15. low-pass filter pop noise each device of the msm6650 family contains a ?pop? nois e killer circuit. however, a low-pass filter selected may cause ?pop? noise as the filter output's circled portions of the figure 15.1 change by approx. 0.7 v abruptly. figure 15.1 pop noise of low-pass filter ?pop? noise can be reduced by connecting a di ode at the aout output (as shown figure 15.2). figure 15.2 pop noise killer circuit standb y conversion time standb y conversion time aout
fedl6650full-06 oki semiconductor msm6650 family 97/126 16. ceramic oscillation figure 16.1 shows an external circuit diagram using a ceramic oscillator. figure 16.1 external circuit diagram figure 16.2 shows an external circuit diagram using a ceramic oscillator, cstls4m09g53-b0 or cstcr4m09g53-r0 made by murata mfg. co., ltd. figure 16.4 shows an extend circuit diagram usi ng a ceramic oscillator, kbr4.0msa/mws/mks/pbrc4.00a made by kyocera corp. when using an oscillator, 4.00 mhz, playback speed is approximately 2% slower than ar204, ar205 analysis tools and demonstration board. figure 16.2 cstls4m09g53-b0 or cstcr4m09g53-r0 figure 16.4 kbr4.0/pbrc4.00a figure 16.5 kbr4.0mws/mks xt xt c1 c2 xt xt internal capacitor xt xt 33 pf 33 pf xt xt internal capacitor
fedl6650full-06 oki semiconductor msm6650 family 98/126 17. power supply (for msm6650) the msm6650 should be powered from a single power sour ce to the analog section and digital section separately, as shown below. the following power connections are not permitted. +5 v dv dd av dd dgnd agnd msm6650 dv dd av dd analog supply digital supply power supply dv dd av dd
fedl6650full-06 oki semiconductor msm6650 family 99/126 18. external rom driving timing (for msm6650) the figure 18.1 shows an external rom driving timing during playback at f osc = 4.096 mhz and f s = 8.0 khz. tables 18.1 and 18.2 show f s data and playback method data, respectively. figure 18.1 external rom driving timing 2 ms (*1) 125 s 4 s 4 s 4 s 4 s 4 s 4 ms about 75 ms (*1) 125 s (*1) 125 s (*1) 125 s (*1) 125 s (*1)(*2) 250 s st (i) nar (o) ce (o) d0-d7 (i) 4 s hereafter, control word & adpcm data address & f s data & playback method data control word adpcm data control word adpcm data 1 byte 255 bytes 1 byte ?. don't care except f s data & playback method data fixed to ?00? all data are created using vo ice analysis edit tool ar204. *1 changes depending on f s . *2 hereafter, ce , d7-d0 are input or output at intervals of 250 s or 125 s. t ced 255 bytes ?. ?. ?.
fedl6650full-06 oki semiconductor msm6650 family 100/126 table 18.1 f sam data o2 o1 o0 sampling frequency (khz) 0 0 0 8.0 0 0 1 10.7 0 1 0 12 8 0 1 1 32.0 1 0 0 4.0 1 0 1 5.3 1 1 0 6.4 1 1 1 16.0 table 18.2 playback method data o7 o6 playback method 0 0 playback by adpcm 0 1 playback by pcm 1 0 playback by melody
fedl6650full-06 oki semiconductor msm6650 family 101/126 application circuits (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx) application circuit in serial input interface mode p1.0 p1.1 p1.2 p2.0 p3.0 reset msm83c154 ch c md msm6652/53/54/55/56 msm6652a/53a/54a/55a/56a/58a msm66p56 i6/sd i5/si st r ese t nar x t xt gnd v dd amp port0 port1 aout i4 i1 i0
fedl6650full-06 oki semiconductor msm6650 family 102/126 (msm6652/53/54/55/56-xxx, msm6652a/53a/54a/55a/56a/58a-xxx, msm66p56-xx) application circuit in parallel input interface mode p2.0 p3.1 p2.2 p2.1 p3.0 reset msm83c154 msm6652/53/54/55/56 msm6652a/53a/54a /55a/56a/58a msm66p56 c h c md st rese t nar xt xt gnd v dd amp p1.6 i6 p1.0 i0 i5 i4 i3 i2 i1 p1.5 p1.4 p1.3 p1.2 p1.1 aout
fedl6650full-06 oki semiconductor msm6650 family 103/126 (msm6650) application circuit in microcontroller interface mode using four 1-mbit eproms (serial input interface) i5/si ra16 ch xt i6/sd nar i0 msm6650 aout cmd i1 i4 rcs ra0 d7 d0 ce ra18 ra17 1b 1a v dd gnd v pp ce oe a16 a0 o7 o0 1y3 1y2 1y1 1y0 2g 1g 74hc139 msm27c101 p2.0 p1.0 p1.1 p1.2 p3.0 reset msm83c154 reset st test1 test2 cpu serial xt v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 av dd dv dd agnd dgnd
fedl6650full-06 oki semiconductor msm6650 family 104/126 (msm6650) application circuit in microcontroller interface mode using four 1-mbit eproms (parallel input interface) v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 v dd gnd v pp ce oe a16 a0 o7 o0 msm27c101 1b 1a 1y3 1y2 1y0 2g 1g 74hc139 1y1 i5/si ra16 xt i6/sd msm6650 aout ra0 d7 d0 ra18 ra17 p2.0 p1.6 p1.5 p1.4 p1.3 reset msm83c154 reset xt av dd dv dd agnd dgnd p1.2 p1.1 p3.0 p2.1 p2.0 p3.1 p1.0 ce i3 i4 i1 i2 i0 nar cmd ch st rcs cpu test1 test2 serial
fedl6650full-06 oki semiconductor msm6650 family 105/126 phrase control table funcion phrase control table the role of phrase control table is to link phrases an d build sentences, which makes an external microcontroller unnecessary. the conventional msm6375 family could not link phrases and synthesis channels in standalone mode, but the msm6650 family can use the phrase control table. for example: the phrase ?today's weather is....? can be used to illustrate the differences between the msm6375 family and msm6650. with the msm6375 family (in stand-alone operation), indi-vidual data must be stored as a phrase in rom (see table1) then for playback each phrase must be addresse d individually. example: ?today?s weather is sunny?, and ?today's weather is rainy?. on the other hand, the msm6650 family has phrase cont rol table functions which el iminate the need for an external microcontroller to provide the continuous timing necessary fo r voice concatenation, as with the msm6375 family. this means that individual phrases or words which are stored in phrase rom can be concatenated in the phrase control table and assigned a single address according to their content. this feature allows for efficient use of memory for phrase storage in rom. table 2 shows phrases/words stored in rom and their addresses, table 3 shows how you can combine the phrase/word addresses (up to a maximum of 8) in the phrase control table to achieve fully concatenated phrases. conventionally data must be repeatedly stored to phrase rom to vocalize ?today?s weather is....?, but overlapped data is not required as shown in table 2 by using phrase control table functions. table 1 conventional phrase rom configuration address [hex] phrase 01 today?s weather is sunny. 02 today?s weather is rainy. 03 today?s weather is sunny becoming cloudy, some areas are rainy. 7f ? ?
fedl6650full-06 oki semiconductor msm6650 family 106/126 table 2 phrase address configuration address [hex] phrase 01 today's 02 weather 03 is 10 sunny 11 cloudy 12 rainy 13 snowy 20 occasional 21 becoming 22 some areas are 7f table 3 phrase control table configuration address [hex] phrase c ontent [max. 8 phrases] 01 [01][02][10][03] 02 [01][02][12][03] 03 [01][02][10][21 ][11][22][13][03] 7f ? ? ? ? ? ?
fedl6650full-06 oki semiconductor msm6650 family 107/126 the phrase control table makes channel synthesis possible, a feature previously not available in standalone mode with the msm6375 family. with phrase control table commands, phrase linking, channel synthesis and ?beep? tone or ?"silence? can be set. a maximum of 8 phrases (16 bytes) per phrase address can be set using the phrase control table feature. table 4 shows the phrase control table configuration. table 4 phrase control table configuration * the word ?phrase? as used here includes any of the following: vo ice, music, beep tones or silence. phrase control table details ? the ?phrase address? consists of up to a maximum of 127 phrases, the ?phrase control table? allows you to choose up to any 8 of th e 127 phrases in the ?phrase address?. the ?phrase control table area? contains both phrase address and phrase control command. each address in the ?phrase control address? can contain up to 8 phrases in the ?phrase c ontrol table?. therefore, each of the 127 phrase control addresses available can represent a single phr ase or up to 8 phrases (for concatenation). the phrase addresss cannot be directly accesse d if the phrase control table is used. phrase control table phrase control address phrase address 1 phrase* command 01 sound data phrase address [ hex ] 01 7f toda y 's 02 03 7e 7f 1 phrase address 2 phrase command 3 phrase command 2 phrase address 3 phrase address 5 phrase address 4 phrase command 4 phrase address 5 phrase command 6 phrase command 6 phrase address 7 phrase command 8 phrase command 7 phrase address 8 phrase address 02 03 04 weathe r is sunn y
fedl6650full-06 oki semiconductor msm6650 family 108/126 figure 1 shows the flowchart when creating an phrase control table using the ar204 and ar205 development tool. figure 1 phrase control table making flowchart phrase control table start beep tone code set 1. specify frequency (0.5, 1.0, 1.3, 2.0 khz) 2. specify sound volume (1/8, 1/4, 1/3, 1/2) 1. voice 2. beep tone 3. silence voice control code set 1. specify channel 2. specify fadeout 3. specify repeat (1, 2, 4, infinite) 4. specify sound volume (0, ?6, ?12, ?18 db) silence insertion code 1. specify channel beep tone time set specify phrase address silence time set phrase control table end? end code set no yes 1 2 3 command data input address data input
fedl6650full-06 oki semiconductor msm6650 family 109/126 1. phrase control table commands table 5 shows the commands that can be set in the phrase control table. table 5 list of phrase control table commands o7 o6 o5 o4 o3 o2 o1 o0 command description 0 0 0 0 0 0 0 0 end code indicates that a piece of set data is completed. ch 0 1 0 0 0 0 0 silence insertion code silence is inserted into the channel designated by ch. ch = ?1? channel 1 ch = ?0? channel 2 after this code is inserted, the silenc e time is set using bits o7 to o0. up to 2.1 seconds can be set. 1 1 0 0 bl1 bl0 bf1 bf0 beep tone code after this code is inserted, the beep tone time is set by using o7 to o0. up 2.1 seconds can be set. ch 1 1 sm rp 1 rp0 vl1 vl0 voice control code silence is inserted into the channel designated by ch. ch = ?1? channel 1 ch = ?0? channel 2 the voice control code sets the number of repeats and sound volume. when the number of repeats is set, sound volume smoothing can also be set. each of the phrase control table commands in table 5 are explained below. bl1 bl0 volume 0 0 1/8 amplitude of channel 1 0 1 1/4 amplitude of channel 1 1 0 1/3 amplitude of channel 1 1 1 1/2 amplitude of channel 1 bf1 bf0 frequency (khz) 0 0 0.5 0 1 1.0 1 0 1.3 1 1 2.0 i4 (sm) volume smoothing during repeating 0 disabled 1 enabled i3 (rp1) i2 (rp0) number of repeats 0 0 1 0 1 2 1 0 4 1 1 infinite i1 (vl1) i0 (vi0) attenuation 0 0 0 db 0 1 ?6 db 1 0 ?12 db 1 1 ?18 db
fedl6650full-06 oki semiconductor msm6650 family 110/126 1.1 end code the end code is used at the completion of a phrase. the msm6650 family recognizes the end code which is necessary when the phrase control table contains only a single phrase. when the maximum number of phrases is selected (8) the end code is unnecessary. 1.2 silence insertion code silence insertion code inserts silence in the specified channel, reducing voice data. o7 o6 o5 o4 o3 o2 o1 o1 ch 0 1 0 0 0 0 0 the channel for silence insertion is specified in the command data, while the silence time is set in the address data. command data bit o7 (ch) specifies into which channel s ilence will be inserted, a ?1? in data bit o7 selects channel 1 while a ?0? selects channel 2. silence time is set at the address settings of phrases shown in table 4. minimum silence time ?. 16.384 ms maximum silence time ?. 2.1 sec. the formula to set the silence time is shown below. t mu = (2 6 (o6) + 2 5 (o5) + 2 4 (o4) + 2 3 (o3) + 2 2 (o2) + 2 1 (o1) + 2 0 (o0)) 16.384 ms table 6 phrase control table example of silence insertion coding o7 o6 o5 o4 o3 o2 o1 o0 1st byte 1 0 1 0 0 0 0 0 silence insertion code 2nd byte 0 0 0 1 1 0 0 0 silence time 3rd byte 0 0 0 0 0 0 0 0 end code 1.3 beep tone code the beep tone code produces a beep tone from an intern al circuit which is independent of the adpcm circuitry. the sound volume and frequency of a beep tone is set in command data, while the playback time of a beep tone is set in the address data. the beep tone can be set only in channel 1. the sound volume is set at data bits o3, o2 and the frequency is set at data bits o1, o0. o7 o6 o5 o4 o3 o2 o1 o1 1 1 0 0 bl1 bl0 bf1 bf0
fedl6650full-06 oki semiconductor msm6650 family 111/126 tables 7 and 8 show the sound volumes and the frequencies that can be set. o3 o2 sound volume o1 o0 frequency 0 0 1/8 amplitude sound volume of channel 1 0 0 0.5 khz 0 1 1/4 amplitude sound volume of channel 1 0 1 1.0 khz 1 0 1/3 amplitude sound volume of channel 1 1 0 1.3 khz 1 1 1/2 amplitude sound volume of channel 1 1 1 2.0 khz the beep tone time is set in the phrase address setting of the phrase control table shown in table 4. minimum beep tone time ?? 16.384 ms maximum beep tone time ?? 2.1 sec. the formula to set a beep tone time is shown below. t be = (2 6 (o6) + 2 5 (o5) + 2 4 (o4) + 2 3 (o3) + 2 2 (o2) + 2 1 (o1) + 2 0 (o0)) 16.384 ms table 9 phrase control table example of beep tone coding o7 o6 o5 o4 o3 o2 o1 o0 1st byte 1 1 0 0 1 1 0 1 beep tone code 2nd byte 0 0 0 1 1 0 0 0 beep tone time 3rd byte 0 0 0 0 0 0 0 0 end code for example, if phrase control data is set as in table 9, a 1.0 khz beep tone is played back at a 1/2 amplitude sound volume in channel 1 for 393 ms. 1.4 voice control code the voice control code sets repeat and sound volume. o7 o6 o5 o4 o3 o2 o1 o1 ch 1 1 sm rp1 rp0 vl1 vl0 the channel is set with data bits ?o7?. if bit ?"o7? is ?h?, channel 1 is select ed, if ?l? channel 2 is set. the voice control condition of each channel is set using bits o0-o4. table 7 sound volume settings table 8 frequency settings
fedl6650full-06 oki semiconductor msm6650 family 112/126 (1) setting the number of repeats the number of repeats is set with data bits o3 and o2, and can be selected from 4 types: 1, 2, 4 and infinite. if infinite is selected, repeat can be stopped by switching to another phrase. table 10 shows the relationship between o3, o2 and the number of repeats. table 10 number of repeats settings o3 o2 number of repeats 0 0 1 0 1 2 1 0 4 1 1 infinite (2) sound volume smoothing during repeat if data bit ?o4? is set to a ?1?, sound volume during repeat is attenuated from 1 to 1/2, 1/4 and 1/8. this smoothing, however, is effective only when 2, 4 or infi nite is selected for the repeat setting. if infinite is selected, voice is played, remaining at 1/8 sound volume after attenuating from 1 to 1/2, 1/4 and 1/8. if the initial sound volume setting is other than 1, the sound volume attenuates from that value in 1/2 units, stopping at 1/8. (3) setting sound volume voice volume can be changed in 4 steps if voice playback overlaps during channel mixing. the sound volume is set with data bits o1 and o0. table 11 show s the corresponding data and attenuation values. table 11 volume attenuation setting o1 o0 volume attenuation 0 0 no attenuation (sound volume is same as voice data) 0 1 ?6 db attenuation (sound volu me is 1/2 of voice data) 1 0 ?12 db attenuation (sound volu me is 1/4 of voice data) 1 1 ?18 db attenuation (sound volu me is 1/8 of voice data)
fedl6650full-06 oki semiconductor msm6650 family 113/126 2. pcm playback using the phrase control table for pcm playback, phrase control table is set together wi th the voice control data. items which can be set in the voice control code include (channel, sound volume smoothing during repeat, number of repeats, and sound volume). 3. melody playback using the phrase control table for melody playback, phrase control table is set togeth er with the voice control data. channels however cannot be set. channel 1 is fixed. channel 2 mixing of melodies is not possible. 4. random playback using the phrase control table if the rnd pin is used during random playback, the 1st phrase control addresss (which consists of an phrase control table sequence up to 8 phrases/16 bytes) is played and the random playback of the 2nd phrase control address then starts random play continuously. random play requires the channel setting for the 1st and 2nd phrase control address to be the same. random play cannot be used during channel 2 play or echo play without the use of the silence insertion technique shown in figure 10 item (2). figure 2 item (1) shows the overlapping of the 2nd phrase control address in channel 1 with the echo playback of channel 2. item (2) shows how silence is inserted after the 1st phrase control address in channel 1 to avoid overlapping of the 2nd phrase cont rol address with channel 2 playback. figure 2 example of random vocalization timing (1) (2) channel 1 channel 2 channel 1 channel 2 1st edit phrase 2nd edit phrase ?today?s? ?weather? ?today?s? silence 1st edit phrase 2nd edit phrase ?today?s? silence ?weather? ?today?s? silence
fedl6650full-06 oki semiconductor msm6650 family 114/126 5. channel 2 mixing function in the phrase control table this function overlaps 2 phrases. by using phrase control table, it is easy to echo a phrase (echo play) and to a phrase with bgm (background music, in channel 2). 5.1 echo playback echo playback delays and overlaps the phrase played in channel 1 at ?6 db attenuation (1/2 amplitude of channel 1) in channel 2. echo playback of a single phrase using address [02] of the phrase rom, ?weather?, an example is shown with echo of a single phrase. table 12 phrase control table example of echo playback of a single phrase o7 o6 o5 o4 o3 o2 o1 o0 1st byte 1 1 1 0 0 0 0 0 voice control code (ch1 select, repeat, ?6 db attenuation) 2nd byte 0 0 0 0 0 0 1 0 phrase address (02h ?weather?) 3rd byte 0 0 1 0 0 0 0 0 silence insertion code (ch2 select) 4th byte 0 0 0 0 0 1 1 0 silence time (98.3 ms) 5th byte 0 1 1 0 0 0 0 1 voice control code (ch2 select, repeat, ?12 db attenuation) 6th byte 0 0 0 0 0 0 1 0 phrase address (02h ?weather?) 7th byte 0 0 0 0 0 0 0 0 end code if phrase control address is set as in table 12, ?weather? is played in channel 1, and is overlapped during playback from channel 2 at ?6 db attenuated sound volume 98.3 ms after the start of channel 1 play. when two phrases overlap set the attenuation of the voice control command with attention to sound volume to prevent clipping. be aware that the silence time is an element that influences the echo quality. set the silence time so that the desired echo is created.
fedl6650full-06 oki semiconductor msm6650 family 115/126 when using echo play set the number of repeats of the voice control command to 1. if 2, 4 or infinite is set, timing becomes as shown in figure 3. (1) number of repeats: 1 (2) number of repeats: 2 (3) number of repeats: 4 (4) number of repeats: infinite figure 3 echo playback timing using repeated playback the echo playback timing, during repeated play which is assigned with the voice control command for an phrase control address, is explained below. channel 1 channel 2 ?weather? ?weather? ?weather? channel 1 has infinite playback channel 2 does not play channel 1 channel 2 ?weather? ?weather? ?weather? ?weather? silence channel 1 channel 2 ?weather? ?weather? ?weather? ?weather? ?weather? ?weather? silence channel 1 channel 2 silence ?weather? ?weather?
fedl6650full-06 oki semiconductor msm6650 family 116/126 (1) when the number of repeats is set to 1 when the same channel is selected fo r playback of the next phrase, playback of the next phrase starts after playback of the 1st phrase ends. if the channel of the next phrase is different (channel 2), then channel synthesis (playback of channels 1 and 2) begins at the start of playback. (2) when the number of repeats is set to 2 when the same channel is selected fo r playback of the next phrase, playback of the next phrase starts after playback of the 2nd phrase ends. if the channel of the next phrase is different (channel 2), then channel synthesis at the start of the second phrase playback. echo does no t occur under these conditions because channels 1 and 2 are played simultaneously. a silence insertion code must be applied to channel 2 for echo to occur, playback in channel 2 is then delayed with respect to channel 1 which causes echo (see figure 3). the amount of echo depends on the duration of the silence in channel 2. (3) when the number of repeats is set to 4 when the same channel is selected fo r playback of the next phrase, playback of the next phrase starts after playback of the 4th phrase ends. if the channel of the next phrase is different (channel 2), then channel synthesis (playback of channels 1 and 2) begins at the start of the 4th phrase playback. echo does not occur under these conditions because channels 1 and 2 are played simultane ously. a silence insertion code must be applied to channel 2 for echo to occur, playback in channel 2 is then delayed with respect to ch annel 1 which causes echo (see figure 3). the amount of echo depends on the duration of the silence in channel 2. (4) when the number of repeats is set to infinite the next phrase becomes invalid and is not played regardless of the channel specification (see figure 3 (4)).
fedl6650full-06 oki semiconductor msm6650 family 117/126 echo playback of multiple phrases a maximum of eight phrases (16-bytes) can be set to the phrase control table area. up to three phrases can be set for echo play with 16 bytes. the phra se rom should be set so that the nu mber of phrases does not exceed four. using ?today?s?, ?weather? and ?is? of the phrase rom in table 2 as an ex ample, table 13 shows echo playback of three phrases. figure 4 shows the playback timing. table 13 phrase control table example-three phrase echo playback o7 o6 o5 o4 o3 o2 o1 o0 1st byte 1 1 1 0 0 0 0 1 voice control code (ch1 select, repeat once, ?6 db attenuation) 2nd byte 0 0 0 0 0 0 0 1 phrase address (01h ?today?s?) 3rd byte 0 0 1 0 0 0 0 0 silence insertion code (ch2 select) 4th byte 0 0 0 0 0 1 1 0 silence time (98.3 ms) 5th byte 0 1 1 0 0 0 1 0 voice control code (ch2 select, repeat once, ?12 db attenuation) 6th byte 0 0 0 0 0 0 0 1 phrase address (01h ?today?s?) 7th byte 1 1 1 0 0 0 0 1 voice control code (ch1 select, repeat once, ?6 db attenuation) 8th byte 0 0 0 0 0 0 1 0 phrase address (02h ?weather?) 9th byte 0 1 1 0 0 0 1 0 voice control code (ch2 select, repeat once, ?12 db attenuation) 10th byte 0 0 0 0 0 0 1 0 phrase address (02h ?weather?) 11th byte 1 1 1 0 0 0 0 1 voice control code (ch1 select, repeat once, ?6 db attenuation) 12th byte 0 0 0 1 0 0 0 0 phrase address (10h ?is?) 13th byte 0 1 1 0 0 0 1 0 voice control code (ch2 select, repeat once, ?12 db attenuation) 14th byte 0 0 0 1 0 0 0 0 phrase address (10h ?is?) 15th byte 1 1 1 0 0 0 1 1 voice control code (ch1 select, repeat once, ?6 db attenuation) 16th byte 0 0 0 0 0 0 1 1 phrase address (03h ?sunny?) figure 4 playback timing of three phrases with echo channel 1 channel 2 ?toda y ?s? ?weather? ?is? ?sunn y ? silence ?toda y ?s? ?weather? ?is?
fedl6650full-06 oki semiconductor msm6650 family 118/126 for the echo playback of multiple phrases, the sampling frequency of each phrase must be the same. if a phrase with a different sampling frequency is mixed, the voice of channel 2 (echo) will be played fast or slow because the sampling frequency of channel has priority. figure 5 shows the timing. figure 5 echo playback timing with different sampling frequencies echo playback of a single phrase within a phrase string table14 shows an phrase control address example to apply ec ho to ?is? in the four phrases of ?today?s?, ?weather?, ?is? and ?sunny?. table 14 phrase control table example of a single phrase within a phrase string o7 o6 o5 o4 o3 o2 o1 o0 1st byte 1 1 1 0 0 0 0 0 voice control code (ch1 select, repeat once, no attenuation) 2nd byte 0 0 0 0 0 0 0 1 phrase address (01h ?today?s?) 3rd byte 0 0 1 0 0 0 0 0 silence insertion code (ch2 select) 4th byte 0 1 1 0 0 0 0 1 silence time (1.59 sec) 5th byte 1 1 1 0 0 0 0 0 voice control code (ch1 select, repeat once, no attenuation) 6th byte 0 0 0 0 0 0 1 0 phrase address (02h ?weather?) 7th byte 1 1 1 0 0 0 0 0 voice control code (ch1 select, repeat once, no attenuation) 8th byte 0 0 0 1 0 0 0 0 phrase address (10h ?is?) 9th byte 0 1 1 0 0 0 0 1 voice control code (ch2 select, repeat once, ?6 db attenuation) 10th byte 0 0 0 1 0 0 0 0 phrase address (10h ?is?) 11th byte 1 1 1 0 0 0 0 0 voice control code (ch1 select, repeat once, no attenuation) 12th byte 0 0 0 0 0 0 1 1 phrase address (03h ?sunny?) 13th byte 0 0 0 0 0 0 0 0 end code channel 1 channel 2 f s = 6.4 khz f s = 8 khz f s = 6.4 khz ?today?s? ?weather? ?is? silence fast playback slow playback ?is? ?today?s? ?weather?
fedl6650full-06 oki semiconductor msm6650 family 119/126 figure 6 playback timing using table 14 phrase control table as shown by the timing in figure 6, ?is? is echoed by setting the silence time to delay playback of channel 2 echo. while channel 1 plays four consecutive phrases, the silence ti me has been set so that channel 2 play is delayed until the selected phrase in channel 1 can be echoed. if the silence time exceeds 2.1 sec, it is necessary to add a silence insertion setting to 2 bytes of the phrase control table. a maximum of 6 phrases are possible if the silence insertion setting is 2 bytes. 5.2 two-channel playback two-channel play uses pcm, memory and adpcm methods. channel mixing is possible with all combinations except melody play/melody play (in channel 2). melody play is in channel 1 only. the sampling frequency of phrases which overlap must be the same. figures 7 to 10 show 2 channel playback timing. figure 7 timing of four phrase channel mixing with a melody tone as bgm (background music) figure 8 timing of four phrase channel mixing with a melody tone for 1st and 4th phrases as bgm (background music) 1.5 sec 0.09 sec channel 1 channel 2 ?today?s? ?weather? ?is? ?sunny? silence ?is? channel 1 channel 2 1st phrase melody tone ?today?s? ?weather? ?is? ?sunny? 2nd phrase 3rd phrase 4th phrase 5th phrase channel 1 channel 2 1st phrase 4th phrase melody tone melody tone ?today?s? ?weather? ?is? ?sunny? 2nd phrase 3rd phrase 5th phrase 6th phrase
fedl6650full-06 oki semiconductor msm6650 family 120/126 figure 9 channel mixing between pcm main melody tone (a) and pcm rhythm tone (b) with 4 repeats figure 10 channel synthesis between pcm main melody tone (a) (b) and pcm rhythm tone (c) (d) with 2 repeats channel 1 channel 2 1st phrase pcm tone (a) pcm tone (b) pcm tone (b) pcm tone (b) pcm tone (b) 2nd phrase channel 1 channel 2 1st phrase 3rd phrase pcm tone (a) pcm tone (b) pcm tone (c) pcm tone (c) pcm tone (d) pcm tone (d) 2nd phrase 4th phrase
fedl6650full-06 oki semiconductor msm6650 family 121/126 package dimensions (unit: mm)
fedl6650full-06 oki semiconductor msm6650 family 122/126 sop24-p-430-1.27-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.58 typ. 5 rev. no./last revised 5/oct. 13, 1998 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl6650full-06 oki semiconductor msm6650 family 123/126 dip20-p-300-2.54-w1 package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.50 typ. 5 rev. no./last revised 2/dec. 11, 1996 ( unit: mm )
fedl6650full-06 oki semiconductor msm6650 family 124/126 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl6650full-06 oki semiconductor msm6650 family 125/126 revision history page document no. date previous edition current edition description fedl6650full-04 nov. 2001 ? ? edition 4 60 60 modified descriptions of ce and rcs . 41 41 changed the part numbers of the ceramic oscillator in fi g ure 14.2. fedl6650full-05 jan. 11, 2002 99 99 changed the part numbers of the ceramic oscillator in fi g ure 16.2. ? ? delete product name of msm66p54 due to discontinuously ? ? delete the explanation about sdip package of msm6650 fedl6650full-06 may 30, 2002 ? ? correct mistake words about phrase control table function
fedl6650full-06 oki semiconductor msm6650 family 126/126 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein has been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right that may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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